公开(公告)号：US20160218053A1

公开(公告)日：2016-07-28

申请号：US14993044

申请日：2016-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Jin CHO ,  Jong-Min JUNG ,  Yun-Ji HUR ,  Sung-Sik PARK ,  Keun-Bong LEE

IPC: H01L23/495

CPC classification number: H01L23/4985 ,  G02F1/13452 ,  H01L23/145 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/00 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A chip-on-film (COF) package includes a base film, a semiconductor chip mounted on a chip mounting region of a top surface of the base film, a plurality of top inner output conductive patterns, a plurality of bottom inner output conductive patterns and a plurality of landing vias. The top inner output conductive patterns are formed on the top surface of the base film and respectively connected to chip inner output pads formed on a bottom surface of the semiconductor chip. The bottom inner output conductive patterns are formed on a bottom surface of the base film. The landing vias are formed to vertically penetrate the base film and to respectively connect the top inner output conductive patterns and the bottom inner output conductive patterns. The landing vias are arranged within the chip mounting region to form a two-dimensional shape.

Abstract translation: 一种片上芯片（COF）封装，包括基膜，安装在基膜的顶表面的芯片安装区域上的半导体芯片，多个顶部内部输出导电图案，多个底部内部输出导电图案 和多个着陆通孔。 顶部内部输出导电图案形成在基底膜的顶表面上并且分别连接到形成在半导体芯片的底表面上的芯片内部输出焊盘。 底部内部输出导电图案形成在基底膜的底表面上。 形成垂直穿过底膜并且分别连接顶部内部输出导电图案和底部内部输出导电图案的着陆通孔。 着陆通孔布置在芯片安装区域内以形成二维形状。