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    SEMICONDUCTOR DEVICES HAVING A STAGGERED PAD WIRING STRUCTURE
    1.
    发明申请
    SEMICONDUCTOR DEVICES HAVING A STAGGERED PAD WIRING STRUCTURE 审中-公开
    具有扁平拼接结构的半导体器件

    公开(公告)号：US20140124923A1

    公开(公告)日：2014-05-08

    申请号：US14072993

    申请日：2013-11-06

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Young-Jin CHO

    IPC: H01L23/498 ,  H01L27/12

    CPC classification number: H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device includes a plurality of first metal wirings of first to n-th layers disposed on a substrate, and a plurality of pad wirings disposed on the first metal wirings and including a metal material of an n+1-th layer. The pad wirings are disposed in a staggered shape in a first direction and have a rectangular shape lengthily extending in a second direction. A plurality of additional wirings are disposed in an additional wiring region in the first direction and include the metal material of the n+1-th layer. The additional wiring region is disposed between the pad wirings. A plurality of pads may contact an upper surface of the pad wirings. The pads have a rectangular shape having a first width in the first direction and a first length greater than the first width in the second direction.

    Abstract translation: 半导体器件包括设置在基板上的第一至第n层的多个第一金属布线和设置在第一金属布线上并包括第n + 1层的金属材料的多个焊盘布线。 衬垫布线沿第一方向以交错形状设置，并且具有沿第二方向长度延伸的矩形形状。 多个附加布线沿第一方向设置在附加布线区域中，并且包括第n + 1层的金属材料。 附加布线区域设置在垫布线之间。 多个焊盘可以接触焊盘布线的上表面。 垫具有在第一方向上具有第一宽度并且第一长度大于第二方向上的第一宽度的矩形形状。

    MEMORY SYSTEM AND ELECTRONIC DEVICE
    3.
    发明申请
    MEMORY SYSTEM AND ELECTRONIC DEVICE 有权
    存储系统和电子设备

    公开(公告)号：US20150363106A1

    公开(公告)日：2015-12-17

    申请号：US14722158

    申请日：2015-05-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sun-Young LIM ,  Dong-Yang LEE ,  Young-Jin CHO ,  Oh-Seong KWON

    IPC: G06F3/06

    CPC classification number: G11C7/10 ,  G06F13/1694 ,  G11C7/1063 ,  G11C7/109

    Abstract: An electronic device includes a memory controller; a first memory device coupled to the memory controller; a second memory device coupled to the memory controller, the second memory device being a different type of memory from the first memory device; and a conversion circuit between the memory controller and the second memory device. The memory controller is configured to send a first command and first data to the first memory device according to a first timing scheme to access the first memory device, and send a second command and a packet to the conversion circuit according to the first timing scheme to access the second memory device. The conversion circuit is configured to receive the second command and the packet, and access the second memory device based on the second command and the packet.

    Abstract translation: 电子设备包括存储器控制器; 耦合到所述存储器控制器的第一存储器件; 耦合到所述存储器控制器的第二存储器设备，所述第二存储器设备是与所述第一存储器设备不同类型的存储器; 以及存储器控制器和第二存储器件之间的转换电路。 存储器控制器被配置为根据第一定时方案向第一存储器设备发送第一命令和第一数据以访问第一存储器件，并且根据第一定时方案向转换电路发送第二命令和数据包到第 访问第二个存储设备。 转换电路被配置为接收第二命令和分组，并且基于第二命令和分组访问第二存储器设备。

    CHIP-ON-FILM PACKAGE AND DISPLAY DEVICE INCLUDING THE SAME
    4.
    发明申请
    CHIP-ON-FILM PACKAGE AND DISPLAY DEVICE INCLUDING THE SAME 有权
    芯片封装和包括其的显示器件

    公开(公告)号：US20160218053A1

    公开(公告)日：2016-07-28

    申请号：US14993044

    申请日：2016-01-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Young-Jin CHO ,  Jong-Min JUNG ,  Yun-Ji HUR ,  Sung-Sik PARK ,  Keun-Bong LEE

    IPC: H01L23/495

    CPC classification number: H01L23/4985 ,  G02F1/13452 ,  H01L23/145 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/00 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A chip-on-film (COF) package includes a base film, a semiconductor chip mounted on a chip mounting region of a top surface of the base film, a plurality of top inner output conductive patterns, a plurality of bottom inner output conductive patterns and a plurality of landing vias. The top inner output conductive patterns are formed on the top surface of the base film and respectively connected to chip inner output pads formed on a bottom surface of the semiconductor chip. The bottom inner output conductive patterns are formed on a bottom surface of the base film. The landing vias are formed to vertically penetrate the base film and to respectively connect the top inner output conductive patterns and the bottom inner output conductive patterns. The landing vias are arranged within the chip mounting region to form a two-dimensional shape.

    Abstract translation: 一种片上芯片（COF）封装，包括基膜，安装在基膜的顶表面的芯片安装区域上的半导体芯片，多个顶部内部输出导电图案，多个底部内部输出导电图案 和多个着陆通孔。 顶部内部输出导电图案形成在基底膜的顶表面上并且分别连接到形成在半导体芯片的底表面上的芯片内部输出焊盘。 底部内部输出导电图案形成在基底膜的底表面上。 形成垂直穿过底膜并且分别连接顶部内部输出导电图案和底部内部输出导电图案的着陆通孔。 着陆通孔布置在芯片安装区域内以形成二维形状。

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