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    LASER ANNEALING APPARATUS
    1.
    发明申请
    LASER ANNEALING APPARATUS 审中-公开

    公开(公告)号：US20180308725A1

    公开(公告)日：2018-10-25

    申请号：US15795746

    申请日：2017-10-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Joong-han SHIN ,  Supakit CHARNVANICHBORIKARN ,  Bong-jin KUH ,  Ki-chul KIM ,  Jae-hee LEE

    IPC: H01L21/67 ,  C30B28/08

    CPC classification number: H01L21/67115 ,  C30B28/08

    Abstract: A laser annealing apparatus includes a laser oscillating structure, an oscillator, a beam expanding telescope, a first power meter, and a second power meter. The laser oscillating structure emits a first laser beam of a first wavelength and first beam cross-section to a substrate in a chamber including an optical window. The oscillator emits a second laser beam, of a second wavelength different from the first wavelength, to the substrate. The beam expanding telescope is on an optical path for the second laser beam and expands the second laser beam to a second beam cross-section. The first and second power meters measure energy of the second laser beam and a third laser beam, generated as the second laser beam is reflected by the substrate. The first beam cross-section and the second beam cross-section may be equal.

    METHODS OF FORMING EPITAXIAL LAYERS
    2.
    发明申请
    METHODS OF FORMING EPITAXIAL LAYERS 有权
    形成外延层的方法

    公开(公告)号：US20140256117A1

    公开(公告)日：2014-09-11

    申请号：US14133944

    申请日：2013-12-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Joong-han SHIN ,  Bong-jin KUH ,  Ki-chul KIM ,  Jeong-meung KIM ,  Eun-ha LEE ,  Jong-sung LIM ,  Han-mei CHOI

    IPC: H01L21/02

    CPC classification number: H01L21/02381 ,  H01L21/02532 ,  H01L21/02667

    Abstract: A method of forming an epitaxial layer includes forming a plurality of first insulation patterns in a substrate, the plurality of first insulation patterns spaced apart from each other, forming first epitaxial patterns on the plurality of first insulation patterns, forming second insulation patterns between the plurality of first insulation patterns to contact the plurality of first insulation patterns, and forming second epitaxial patterns on the second insulation patterns and between the first epitaxial patterns to contact the first epitaxial patterns, the first epitaxial patterns and the second epitaxial patterns forming a single epitaxial layer.

    Abstract translation: 形成外延层的方法包括在基板中形成多个第一绝缘图案，多个第一绝缘图案彼此间隔开，在多个第一绝缘图案上形成第一外延图案，在多个第一绝缘图案之间形成第二绝缘图案 的第一绝缘图案以接触所述多个第一绝缘图案，以及在所述第二绝缘图案上和所述第一外延图案之间以及所述第一外延图案之间形成第二外延图案以接触所述第一外延图案，所述第一外延图案和所述第二外延图案形成单个外延层 。

    SEMICONDUCTOR DEVICE HAVING REDUCED-DAMAGE ACTIVE REGION AND METHOD OF MANUFACTURING THE SAME
    3.
    发明申请
    SEMICONDUCTOR DEVICE HAVING REDUCED-DAMAGE ACTIVE REGION AND METHOD OF MANUFACTURING THE SAME 审中-公开
    具有减少损伤活性区域的半导体器件及其制造方法

    公开(公告)号：US20150140749A1

    公开(公告)日：2015-05-21

    申请号：US14607804

    申请日：2015-01-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ki-chul KIM

    IPC: H01L21/8238

    CPC classification number: H01L21/823878 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/7843

    Abstract: A semiconductor device according to example embodiments may include a substrate having an NMOS area and a PMOS area, isolation regions and well regions formed in the substrate, gate patterns formed on the substrate between the isolation regions, source/drain regions formed in the substrate between the gate patterns and the isolation regions, source/drain silicide regions formed in the source/drain regions, a tensile stress layer formed on the NMOS area, and a compressive stress layer formed on the PMOS area, wherein the tensile stress layer and compressive stress layer may overlap at a boundary region of the NMOS area and the PMOS area. The semiconductor devices according to example embodiments and methods of manufacturing the same may increase the stress effect on the active region while reducing or preventing surface damage to the active region.

    Abstract translation: 根据示例实施例的半导体器件可以包括具有NMOS区域和PMOS区域的衬底，形成在衬底中的隔离区域和阱区域，形成在隔离区域之间的衬底上的栅极图案，在衬底中形成的源极/漏极区域 源极/漏极区域中形成的栅极图案和隔离区域，源极/漏极硅化物区域，形成在NMOS区域上的拉伸应力层和形成在PMOS区域上的压应力层，其中拉伸应力层和压应力 层可以在NMOS区域和PMOS区域的边界区域处重叠。 根据示例性实施例的半导体器件及其制造方法可以增加对有源区域的应力作用，同时减少或防止对有源区域的表面损伤。

    ELECTRONIC APPARATUS AND CONTROL METHOD THEREOF
    6.
    发明申请
    ELECTRONIC APPARATUS AND CONTROL METHOD THEREOF 审中-公开

    公开(公告)号：US20190227988A1

    公开(公告)日：2019-07-25

    申请号：US16190738

    申请日：2018-11-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sun-beom KWON ,  Ki-chul KIM ,  Han-nam KIM ,  Su-jin CHO

    IPC: G06F16/16 ,  H04N1/21 ,  H04N5/232 ,  G06K9/00

    Abstract: An electronic apparatus is provided. The electronic apparatus includes a camera, a storage, and a processor configured to store an image photographed by the camera and metadata of the image in the storage, the processor is further configured to identify whether first information related to the image is obtainable, based on the first information not being obtainable, generate metadata related to the first information based on second information, and store the generated metadata as metadata of the image.

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