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    System-on-chip for at-speed test of logic circuit and operating method thereof
    5.
    发明授权
    System-on-chip for at-speed test of logic circuit and operating method thereof 有权

    公开(公告)号：US10969432B2

    公开(公告)日：2021-04-06

    申请号：US16544160

    申请日：2019-08-19

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Beom Seok Shin ,  Jinsoo Park

    IPC: G01R31/3185 ,  G01R31/3177 ,  G01R31/317

    Abstract: A system-on-chip includes a first scan register being in a first core and being closest to an input port of the first core; an inverting circuit on a feedback path of the first scan register; a second scan register in the first core; and a logic circuit on a data path between the first scan register and the second scan register. In a test mode for an AT-SPEED test of the logic circuit, the inverting circuit generates test data by inverting scan data that are output from the first scan register, the first scan register stores the test data in response to a first pulse of a clock signal, the logic circuit generates result data based on the test data that are output from the first scan register, and the second scan register stores the result data in response to a second pulse of the clock signal.

    LINE INTERLEAVING CONTROLLER, IMAGE SIGNAL PROCESSOR AND APPLICATION PROCESSOR INCLUDING THE SAME
    8.
    发明申请
    LINE INTERLEAVING CONTROLLER, IMAGE SIGNAL PROCESSOR AND APPLICATION PROCESSOR INCLUDING THE SAME 有权

    公开(公告)号：US20230088614A1

    公开(公告)日：2023-03-23

    申请号：US18059607

    申请日：2022-11-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kilhyung CHA ,  Jinsoo Park ,  Dongwoo Lee ,  Serhoon Lee ,  Sungjin Huh

    IPC: G06T1/20 ,  G06T1/60 ,  G06F9/54 ,  G06F13/42 ,  G06F13/16

    Abstract: An image signal processor includes a line interleaving controller and an image signal processor core. The line interleaving controller receives a plurality of image data lines included in an image frame, generates one or more virtual data lines corresponding to the image frame, and outputs the plurality of image data lines and the virtual data lines sequentially line by line. The image signal processor core includes at least one pipeline circuit. The pipe line circuit includes a plurality of processing modules serially connected to sequentially process data lines received from the line interleaving controller. The line interleaving controller processes one or more end image data lines included in an end portion of the image frame based on the virtual data lines. Interference or collision between channels is reduced or prevented by processing the end image data lines in synchronization with the virtual data lines.

    System-on-chip for AT-SPEED test of logic circuit and operating method thereof
    9.
    发明授权
    System-on-chip for AT-SPEED test of logic circuit and operating method thereof 有权

    公开(公告)号：US11442107B2

    公开(公告)日：2022-09-13

    申请号：US17206288

    申请日：2021-03-19

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Beom Seok Shin ,  Jinsoo Park

    IPC: G01R31/3185 ,  G01R31/3177 ,  G01R31/317

    Abstract: A system-on-chip includes a first scan register being in a first core and being closest to an input port of the first core; an inverting circuit on a feedback path of the first scan register; a second scan register in the first core; and a logic circuit on a data path between the first scan register and the second scan register. In a test mode for an AT-SPEED test of the logic circuit, the inverting circuit generates test data by inverting scan data that are output from the first scan register, the first scan register stores the test data in response to a first pulse of a clock signal, the logic circuit generates result data based on the test data that are output from the first scan register, and the second scan register stores the result data in response to a second pulse of the clock signal.

    Apparatus in synchronization system and methods for operating the same
    10.
    发明授权
    Apparatus in synchronization system and methods for operating the same 有权

    公开(公告)号：US11523362B2

    公开(公告)日：2022-12-06

    申请号：US16733650

    申请日：2020-01-03

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jinsoo Park ,  Hyunpyo Lee ,  Byoungkon Park ,  Jaeyoon Lee ,  Seungpyo Han

    IPC: H04W56/00

    Abstract: The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as Long Term Evolution (LTE). The disclosure is A first apparatus for estimating a delay time in a synchronization system is provided. The first apparatus includes a detector configured to detect a request signal generated by a second apparatus, and a generator configured to generate a response signal corresponding to the request signal and output the response signal. The request signal is received through a cable from the second apparatus and the response signal is transmitted to the second apparatus through the cable.

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