公开(公告)号：US11869116B2

公开(公告)日：2024-01-09

申请号：US18059607

申请日：2022-11-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kilhyung Cha ,  Jinsoo Park ,  Dongwoo Lee ,  Serhoon Lee ,  Sungjin Huh

IPC: G06T15/00 ,  G06T1/20 ,  G06T1/60 ,  G06F9/54 ,  G06F13/42 ,  G06F13/16

CPC classification number: G06T1/20 ,  G06F9/544 ,  G06F13/1647 ,  G06F13/4282 ,  G06T1/60

Abstract: An image signal processor includes a line interleaving controller and an image signal processor core. The line interleaving controller receives a plurality of image data lines included in an image frame, generates one or more virtual data lines corresponding to the image frame, and outputs the plurality of image data lines and the virtual data lines sequentially line by line. The image signal processor core includes at least one pipeline circuit. The pipe line circuit includes a plurality of processing modules serially connected to sequentially process data lines received from the line interleaving controller. The line interleaving controller processes one or more end image data lines included in an end portion of the image frame based on the virtual data lines. Interference or collision between channels is reduced or prevented by processing the end image data lines in synchronization with the virtual data lines.

公开(公告)号：US20230088614A1

公开(公告)日：2023-03-23

申请号：US18059607

申请日：2022-11-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kilhyung CHA ,  Jinsoo Park ,  Dongwoo Lee ,  Serhoon Lee ,  Sungjin Huh

IPC: G06T1/20 ,  G06T1/60 ,  G06F9/54 ,  G06F13/42 ,  G06F13/16

Abstract: An image signal processor includes a line interleaving controller and an image signal processor core. The line interleaving controller receives a plurality of image data lines included in an image frame, generates one or more virtual data lines corresponding to the image frame, and outputs the plurality of image data lines and the virtual data lines sequentially line by line. The image signal processor core includes at least one pipeline circuit. The pipe line circuit includes a plurality of processing modules serially connected to sequentially process data lines received from the line interleaving controller. The line interleaving controller processes one or more end image data lines included in an end portion of the image frame based on the virtual data lines. Interference or collision between channels is reduced or prevented by processing the end image data lines in synchronization with the virtual data lines.

公开(公告)号：US11514552B2

公开(公告)日：2022-11-29

申请号：US17136494

申请日：2020-12-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kilhyung Cha ,  Jinsoo Park ,  Dongwoo Lee ,  Serhoon Lee ,  Sungjin Huh

IPC: G06T15/00 ,  G06T1/20 ,  G06T1/60 ,  G06F9/54 ,  G06F13/42 ,  G06F13/16

Abstract: An image signal processor includes a line interleaving controller and an image signal processor core. The line interleaving controller receives a plurality of image data lines included in an image frame, generates one or more virtual data lines corresponding to the image frame, and outputs the plurality of image data lines and the virtual data lines sequentially line by line. The image signal processor core includes at least one pipeline circuit. The pipe line circuit includes a plurality of processing modules serially connected to sequentially process data lines received from the line interleaving controller. The line interleaving controller processes one or more end image data lines included in an end portion of the image frame based on the virtual data lines. Interference or collision between channels is reduced or prevented by processing the end image data lines in synchronization with the virtual data lines.

公开(公告)号：US11223762B2

公开(公告)日：2022-01-11

申请号：US17060761

申请日：2020-10-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kilhyung Cha ,  Dongwoo Lee ,  Serhoon Lee ,  Kyungah Jeong ,  Sungjin Huh

IPC: H04N5/232

Abstract: A device includes an image sensor configured to generate a first signal corresponding to an image having a first resolution in a first mode, a second signal corresponding to an image having a second resolution higher than the first resolution in a second mode. The image sensor is configured to generate frame information regarding a resolution, the first mode and the second mode respectively determined based on a mode signal. The device further includes a channel allocator configured to allocate the first signal and the second signal to different channels, of a plurality of channels, based on the frame information; and an image signal processor (ISP) comprising the plurality of channels, a first channel configured to process the first signal and a second channel configured to process the second signal. The ISP is configured to post-process image data processed by the plurality of channels.

公开(公告)号：US20210176396A1

公开(公告)日：2021-06-10

申请号：US17060761

申请日：2020-10-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kilhyung Cha ,  Dongwoo Lee ,  Serhoon Lee ,  Kyungah Jeong ,  Sungjin Huh

IPC: H04N5/232

Abstract: A device includes an image sensor configured to generate a first signal corresponding to an image having a first resolution in a first mode, a second signal corresponding to an image having a second resolution higher than the first resolution in a second mode. The image sensor is configured to generate frame information regarding a resolution, the first mode and the second mode respectively determined based on a mode signal. The device further includes a channel allocator configured to allocate the first signal and the second signal to different channels, of a plurality of channels, based on the frame information; and an image signal processor (ISP) comprising the plurality of channels, a first channel configured to process the first signal and a second channel configured to process the second signal. The ISP is configured to post-process image data processed by the plurality of channels.