公开(公告)号：US20190157273A1

公开(公告)日：2019-05-23

申请号：US16253291

申请日：2019-01-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Nam-gun KIM ,  Sang-min LEE ,  Tae-seop CHOI ,  Kon HA ,  Seung-jae LEE

IPC: H01L27/108 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/522

Abstract: A semiconductor device includes a substrate with an active region, a plurality of conductive line structures on the substrate, an insulating layer separating the plurality of conductive line structures from the substrate, a contact plug between every two adjacent conductive line structures, an insulating spacer structure between each conductive line structure and a corresponding contact plug, a landing pad connected to each contact plug, and a landing pad insulation pattern having an asymmetrical shape based on a vertical axis of the landing pad that extends along a normal to the substrate. The landing pad insulation pattern includes a first portion overlapping the conductive line structures and a second portion overlapping the contact plug, the first and second portions being on opposite sides of the vertical axis.

公开(公告)号：US20180047732A1

公开(公告)日：2018-02-15

申请号：US15598570

申请日：2017-05-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Nam-gun KIM ,  Sang-min LEE ,  Tae-seop CHOI ,  Kon HA ,  Seung-jae LEE

IPC: H01L27/108 ,  H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L27/10814 ,  H01L21/76801 ,  H01L21/76841 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/5329 ,  H01L27/10847 ,  H01L27/10855 ,  H01L27/10888

Abstract: A semiconductor device includes a substrate with an active region, a plurality of conductive line structures on the substrate, an insulating layer separating the plurality of conductive line structures from the substrate, a contact plug between every two adjacent conductive line structures, an insulating spacer structure between each conductive line structure and a corresponding contact plug, a landing pad connected to each contact plug, and a landing pad insulation pattern separating every two adjacent landing pads from each other, each of the landing pad insulation patterns having an asymmetrical shape based on a vertical axis of the landing pad that extends along a normal to the substrate.

公开(公告)号：US20180033637A1

公开(公告)日：2018-02-01

申请号：US15443370

申请日：2017-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Nam-Gun KIM ,  Sangmin LEE ,  Sinhae DO ,  Seok-Won CHO ,  Taeseop CHOI ,  Kon HA

IPC: H01L21/311 ,  H01L21/033 ,  G03F7/20 ,  H01L21/308

CPC classification number: H01L21/31116 ,  G03F7/70033 ,  H01L21/0332 ,  H01L21/3081 ,  H01L21/31144 ,  H01L27/10894

Abstract: Example embodiments relate to a method for fabricating a semiconductor device. The method for fabricating a semiconductor device includes stacking on a substrate an etching target layer, a first mask layer, and a photoresist layer, irradiating extreme ultraviolet (EUV) radiation on the photoresist layer to form a photoresist pattern, patterning the first mask layer to form a first mask pattern using the photoresist pattern as an etching mask, and patterning the etching target layer to form a target pattern using the first mask pattern as an etching mask. The first mask layer includes at least one of a silicon layer and a titanium oxide layer.