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公开(公告)号:US20170316950A1
公开(公告)日:2017-11-02
申请号:US15444381
申请日:2017-02-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Kyungmun BYUN , Sinhae DO , Badro IM
IPC: H01L21/308 , H01L21/3213 , H01L21/28
CPC classification number: H01L21/3086 , H01L21/0337 , H01L21/28017 , H01L21/32139
Abstract: A method for forming patterns of a semiconductor device includes sequentially forming a hard mask layer, a sacrificial layer, and an anti-reflection layer on a substrate, the substrate including a cell region and a peripheral circuit region, patterning the sacrificial layer to form a first sacrificial pattern on the cell region and a second sacrificial pattern on the peripheral circuit region, forming spacers covering sidewalls of the first and second sacrificial patterns, and removing the first sacrificial pattern. The anti-reflection layer includes a lower anti-reflection layer and an upper anti-reflection layer which are formed of materials different from each other. In the patterning of the sacrificial layer, the anti-reflection layer is patterned to form a first anti-reflection pattern on the first sacrificial pattern and a second anti-reflection pattern on the second sacrificial pattern. The second anti-reflection pattern remains when the first sacrificial pattern is removed.
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公开(公告)号:US20180033637A1
公开(公告)日:2018-02-01
申请号:US15443370
申请日:2017-02-27
Applicant: Samsung Electronics Co., Ltd.
Inventor: Nam-Gun KIM , Sangmin LEE , Sinhae DO , Seok-Won CHO , Taeseop CHOI , Kon HA
IPC: H01L21/311 , H01L21/033 , G03F7/20 , H01L21/308
CPC classification number: H01L21/31116 , G03F7/70033 , H01L21/0332 , H01L21/3081 , H01L21/31144 , H01L27/10894
Abstract: Example embodiments relate to a method for fabricating a semiconductor device. The method for fabricating a semiconductor device includes stacking on a substrate an etching target layer, a first mask layer, and a photoresist layer, irradiating extreme ultraviolet (EUV) radiation on the photoresist layer to form a photoresist pattern, patterning the first mask layer to form a first mask pattern using the photoresist pattern as an etching mask, and patterning the etching target layer to form a target pattern using the first mask pattern as an etching mask. The first mask layer includes at least one of a silicon layer and a titanium oxide layer.
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