公开(公告)号：US10817637B2

公开(公告)日：2020-10-27

申请号：US15643472

申请日：2017-07-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Naya Ha ,  Yong-Durk Kim ,  Bong-hyun Lee ,  Hyung-ock Kim ,  Kwang-ok Jeong ,  Jae-hoon Kim

IPC: G06F30/392 ,  G06F30/394 ,  G06F30/398 ,  G06F119/06 ,  G06F119/10 ,  G06F119/12 ,  G06F119/18

Abstract: A system and method of designing an integrated circuit (IC) by considering a local layout effect are provided. The method of designing an IC may place instances of pre-placement cells so as to decrease occurrence of a local layout effect (LLE) causing structure. The method may extract a context of an instance from a peripheral layout of each of the placed instances to estimate an LLE of the instance, thereby analyzing a performance of the IC.