公开(公告)号：US20180231604A1

公开(公告)日：2018-08-16

申请号：US15842184

申请日：2017-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-il Kim ,  Jae-hoon Kim ,  Hyung-ock Kim ,  Jung-yun Choi

IPC: G01R31/28 ,  G06F17/50

CPC classification number: G01R31/2851 ,  G06F17/505 ,  G06F17/5054 ,  G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/84

Abstract: Computer implemented methods of designing integrated circuits and computing systems are provided. A computer implemented method of designing an integrated circuit according to the inventive concepts may be performed by a processor and may include performing a placement and routing (P&R) operation for standard cells defining the integrated circuit, extracting characteristic values from a result of the P&R operation, generating a physical-aware annotation file by determining a plurality of representative characteristic values that respectively correspond to a plurality of groups based on the extracted characteristic values, and performing a physical-aware synthesis operation to generate a netlist from input data for the integrated circuit, based on the generated physical-aware annotation file.

公开(公告)号：US10928442B2

公开(公告)日：2021-02-23

申请号：US15842184

申请日：2017-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-il Kim ,  Jae-hoon Kim ,  Hyung-ock Kim ,  Jung-yun Choi

IPC: G01R31/28 ,  G06F30/34 ,  G06F30/327 ,  G06F30/392 ,  G06F30/398 ,  G06F30/394 ,  G06F119/12

Abstract: Computer implemented methods of designing integrated circuits and computing systems are provided. A computer implemented method of designing an integrated circuit according to the inventive concepts may be performed by a processor and may include performing a placement and routing (P&R) operation for standard cells defining the integrated circuit, extracting characteristic values from a result of the P&R operation, generating a physical-aware annotation file by determining a plurality of representative characteristic values that respectively correspond to a plurality of groups based on the extracted characteristic values, and performing a physical-aware synthesis operation to generate a netlist from input data for the integrated circuit, based on the generated physical-aware annotation file.

公开(公告)号：US10817637B2

公开(公告)日：2020-10-27

申请号：US15643472

申请日：2017-07-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Naya Ha ,  Yong-Durk Kim ,  Bong-hyun Lee ,  Hyung-ock Kim ,  Kwang-ok Jeong ,  Jae-hoon Kim

IPC: G06F30/392 ,  G06F30/394 ,  G06F30/398 ,  G06F119/06 ,  G06F119/10 ,  G06F119/12 ,  G06F119/18

Abstract: A system and method of designing an integrated circuit (IC) by considering a local layout effect are provided. The method of designing an IC may place instances of pre-placement cells so as to decrease occurrence of a local layout effect (LLE) causing structure. The method may extract a context of an instance from a peripheral layout of each of the placed instances to estimate an LLE of the instance, thereby analyzing a performance of the IC.