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    System and method of analyzing integrated circuit in consideration of a process variation and a shift
    3.
    发明授权
    System and method of analyzing integrated circuit in consideration of a process variation and a shift 有权

    公开(公告)号：US11256846B2

    公开(公告)日：2022-02-22

    申请号：US16404910

    申请日：2019-05-07

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Moon-Su Kim ,  Naya Ha ,  Jong-Ku Kang ,  Andrew Paul Hoover

    IPC: G06F30/398 ,  G06F30/327 ,  G06F119/12

    Abstract: A computer implemented method for analyzing a timing of an integrated circuit, wherein an interconnection of a first net of the integrated circuit includes at least one conducting segment formed in a wiring layer or a via layer, includes obtaining a plurality of resistances and a plurality of capacitances, which correspond to each of the at least one conducting segment, based on a process variation, counting a number of layers in which the at least one conducting segments is formed, and calculating a corner resistance and a corner capacitance of the first net, based on the number of layers, the plurality of resistances, and the plurality of capacitances, wherein the counting of the number of layers includes calculating an effective number of layers based on a resistance variability and/or a capacitance variability of each of the layers.

    SYSTEM AND METHOD OF ANALYZING INTEGRATED CIRCUIT IN CONSIDERATION OF A PROCESS VARIATION
    4.
    发明申请
    SYSTEM AND METHOD OF ANALYZING INTEGRATED CIRCUIT IN CONSIDERATION OF A PROCESS VARIATION 审中-公开
    分析综合电路的系统与方法考虑过程变化

    公开(公告)号：US20160283643A1

    公开(公告)日：2016-09-29

    申请号：US15081291

    申请日：2016-03-25

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Moon-Su Kim ,  Naya Ha ,  Jong-Ku Kang ,  Andrew Paul Hoover

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G06F17/5031 ,  G06F2217/82 ,  G06F2217/84

    Abstract: A method of analyzing an integrated circuit, which is implemented by a computing system or a processor, wherein an interconnection of a first net of the integrated circuit includes at least one conducting segment corresponding to one wiring layer or one via, includes receiving a plurality of resistances and a plurality of capacitances, which correspond to the first net, based on a process variation, counting a number of conducting segments corresponding to the first net, and calculating a first resistance or a first capacitance of the first net, based on the number of conducting segments, the plurality of resistances, and the plurality of capacitances.

    Abstract translation: 一种分析由计算系统或处理器实现的集成电路的方法，其中集成电路的第一网络的互连包括对应于一个布线层或一个通孔的至少一个导电段，包括接收多个 基于处理变化，对应于第一网的电阻和多个电容，对与第一网相对应的导电段的数量进行计数，以及基于第一网的数量计算第一网的第一电阻或第一电容 的导电段，多个电阻和多个电容。

    SYSTEM AND METHOD OF ANALYZING INTEGRATED CIRCUIT IN CONSIDERATION OF A PROCESS VARIATION AND A SHIFT
    5.
    发明申请
    SYSTEM AND METHOD OF ANALYZING INTEGRATED CIRCUIT IN CONSIDERATION OF A PROCESS VARIATION AND A SHIFT 审中-公开

    公开(公告)号：US20190258775A1

    公开(公告)日：2019-08-22

    申请号：US16404910

    申请日：2019-05-07

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： MOON-SU KIM ,  Naya Ha ,  Jong-ku Kang ,  Andrew Paul Hoover

    IPC: G06F17/50

    Abstract: A computer implemented method for analyzing a timing of an integrated circuit, wherein an interconnection of a first net of the integrated circuit includes at least one conducting segment formed in a wiring layer or a via layer, includes obtaining a plurality of resistances and a plurality of capacitances, which correspond to each of the at least one conducting segment, based on a process variation, counting a number of layers in which the at least one conducting segments is formed, and calculating a corner resistance and a corner capacitance of the first net, based on the number of layers, the plurality of resistances, and the plurality of capacitances, wherein the counting of the number of layers includes calculating an effective number of layers based on a resistance variability and/or a capacitance variability of each of the layers.

    System and method of analyzing integrated circuit in consideration of a process variation
    6.
    发明授权
    System and method of analyzing integrated circuit in consideration of a process variation 有权

    公开(公告)号：US10372869B2

    公开(公告)日：2019-08-06

    申请号：US15081291

    申请日：2016-03-25

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Moon-Su Kim ,  Naya Ha ,  Jong-Ku Kang ,  Andrew Paul Hoover

    IPC: G06F17/50

    Abstract: A method of analyzing an integrated circuit, which is implemented by a computing system or a processor, wherein an interconnection of a first net of the integrated circuit includes at least one conducting segment corresponding to one wiring layer or one via, includes receiving a plurality of resistances and a plurality of capacitances, which correspond to the first net, based on a process variation, counting a number of conducting segments corresponding to the first net, and calculating a first resistance or a first capacitance of the first net, based on the number of conducting segments, the plurality of resistances, and the plurality of capacitances.

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