公开(公告)号：US20190057179A1

公开(公告)日：2019-02-21

申请号：US15998852

申请日：2018-08-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bong-hyun Lee

IPC: G06F17/50 ,  H03K3/037

Abstract: An integrated circuit (IC) including a first synchronous circuit configured to operate in synchronization with a clock signal is provided. The first synchronous circuit includes a selector including a first input terminal configured to receive a first input signal, a second input terminal configured to receive a second input signal, and a third input terminal configured to receive a scan enable signal indicating one of a scan test mode and a function operation mode and a latch unit configured to operate as a flip-flop outputting a first output signal corresponding to the first input signal in the scan test mode and to operate as a latch outputting a second output signal corresponding to the second input signal in the function operation mode.

公开(公告)号：US10817637B2

公开(公告)日：2020-10-27

申请号：US15643472

申请日：2017-07-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Naya Ha ,  Yong-Durk Kim ,  Bong-hyun Lee ,  Hyung-ock Kim ,  Kwang-ok Jeong ,  Jae-hoon Kim

IPC: G06F30/392 ,  G06F30/394 ,  G06F30/398 ,  G06F119/06 ,  G06F119/10 ,  G06F119/12 ,  G06F119/18

Abstract: A system and method of designing an integrated circuit (IC) by considering a local layout effect are provided. The method of designing an IC may place instances of pre-placement cells so as to decrease occurrence of a local layout effect (LLE) causing structure. The method may extract a context of an instance from a peripheral layout of each of the placed instances to estimate an LLE of the instance, thereby analyzing a performance of the IC.

公开(公告)号：US10699054B2

公开(公告)日：2020-06-30

申请号：US15998852

申请日：2018-08-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bong-hyun Lee

IPC: H03K3/037 ,  G06F30/398 ,  G06F30/327 ,  G06F30/392 ,  G06F30/394 ,  G06F30/3312 ,  G06F30/34 ,  G06F30/333 ,  G06F119/12

Abstract: An integrated circuit (IC) including a first synchronous circuit configured to operate in synchronization with a clock signal is provided. The first synchronous circuit includes a selector including a first input terminal configured to receive a first input signal, a second input terminal configured to receive a second input signal, and a third input terminal configured to receive a scan enable signal indicating one of a scan test mode and a function operation mode and a latch unit configured to operate as a flip-flop outputting a first output signal corresponding to the first input signal in the scan test mode and to operate as a latch outputting a second output signal corresponding to the second input signal in the function operation mode.