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    MEMORY DEVICE HAVING SUB WORDLINE DRIVER
    3.
    发明申请
    MEMORY DEVICE HAVING SUB WORDLINE DRIVER 有权

    公开(公告)号：US20230122198A1

    公开(公告)日：2023-04-20

    申请号：US17724006

    申请日：2022-04-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Myeongsik RYU ,  Bokyeon WON ,  Kyoungmin KIM ,  Donggeon KIM ,  Sangwook PARK ,  Inseok BAEK

    IPC: G11C11/408

    Abstract: A memory device includes a first sub wordline driver including a first active region connected to a first wordline through a first direct contact, and a first transistor connected to a first gate line, the first gate line and the first wordline extending in a first direction, and a second sub wordline driver including a second active region connected to a second wordline through a second direct, the second direct contact and first direct contact extending in parallel in a second direction, the second direction being perpendicular to the first direction. A second transistor is connected to a second gate line. The second gate line extends in the first direction. A third wordline driven by a third sub wordline driver is between the first wordline and the second wordline.

    INTEGRATED CIRCUIT DEVICES
    6.
    发明申请
    INTEGRATED CIRCUIT DEVICES 有权

    公开(公告)号：US20220076732A1

    公开(公告)日：2022-03-10

    申请号：US17245334

    申请日：2021-04-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Taesung KANG ,  Youngkyu LEE ,  Kyoungmin KIM ,  Ilgweon KIM ,  Bokyeon WON ,  Seokjae LEE ,  Sungho JANG ,  Joon HAN

    IPC: G11C11/4091 ,  H01L27/108

    Abstract: An integrated circuit device includes a sense amplifier configured to sense a voltage change of a bit line, wherein the sense amplifier includes: a sense amplifier unit connected to the bit line and a complementary bit line, configured to sense the voltage change of the bit line in response to a control signal, configured to adjust voltages of a sensing bit line and a complementary sensing bit line based on the sensed voltage change, and including a first PMOS transistor and a first NMOS transistor; and a first offset canceling unit connecting the bit line to the complementary sensing bit line in response to an offset canceling signal, and including a first offset canceling transistor arranged between the first NMOS transistor and the first PMOS transistor, wherein the first offset canceling transistor shares a common impurity region with the first NMOS transistor.

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