公开(公告)号：US20220139429A1

公开(公告)日：2022-05-05

申请号：US17465429

申请日：2021-09-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seok Jae LEE ,  Bok-Yeon WON ,  Kyoung Min KIM ,  Dong Geon KIM ,  Myeong Sik RYU ,  In Seok BAEK

IPC: G11C7/06

Abstract: A sense amplifier includes a bit line sense amplifier including a first transistor and a second transistor spaced apart from each other in a first direction, a second conductive line configured to electrically connect the first transistor to the second transistor and extending in the first direction and a local sense amplifier configured to at least partially overlap the second conductive line and disposed between the first transistor and the second transistor. The local sense amplifier includes an active region, a plurality of gate patterns at least partially extending in the first direction and disposed on the active region, a first contact disposed between the plurality of gate patterns and including a long side extending in the first direction and a short side extending in a second direction crossing the first direction and a first conductive line electrically connected to the first contact while overlapping the first contact in a plan view and including a first conductive region extending in the first direction.

公开(公告)号：US20180174959A1

公开(公告)日：2018-06-21

申请号：US15677054

申请日：2017-08-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Ju KIM ,  Su-A KIM ,  Soo-Young KIM ,  Min-Woo WON ,  Bok-Yeon WON ,  Ji-Suk KWON ,  Young-Ho KIM ,  Ji-Hak YU ,  Hyun-Chul YOON ,  Seok-Jae LEE ,  Sang-Keun HAN ,  Woong-Dai KANG ,  Hyuk-Joon KWON ,  Bum-Jae LEE

IPC: H01L23/522 ,  H01L23/50 ,  H01L23/552 ,  H01L23/528 ,  H01L23/00

CPC classification number: H01L23/5225 ,  G11C7/06 ,  G11C7/1057 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4097 ,  H01L23/50 ,  H01L23/5226 ,  H01L23/5286 ,  H01L23/552 ,  H01L24/06 ,  H01L24/20 ,  H01L2224/02331 ,  H01L2224/02373 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/04105 ,  H01L2224/06155 ,  H01L2224/06159 ,  H01L2224/12105 ,  H01L2924/18162 ,  H01L2924/3025

Abstract: A memory device including a memory cell array region, includes, column selection signal lines formed in a first column conduction layer of the memory cell array region and extending in a column direction, global input-output data lines formed in a second column conduction layer of the memory cell array region different from the first column conduction layer and extending in the column direction and power lines formed in a shield conduction layer of the memory cell array region between the first column conduction layer and the second column conduction layer. The noises in the signal lines and the power lines may be reduced and performance of the memory device may be enhanced by forming the column selection signal lines and the global input-output data lines in different column conduction layers and forming the power lines in the shield conduction layer between the column conduction layers.

公开(公告)号：US20240221824A1

公开(公告)日：2024-07-04

申请号：US18607646

申请日：2024-03-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soo Bong CHANG ,  Young-Il LIM ,  Bok-Yeon WON ,  Seok Jae LEE ,  Dong Geon KIM ,  Myeong Sik RYU ,  In Seok BAEK ,  Kyoung Min KIM ,  Sang Wook PARK

IPC: G11C11/4091 ,  G11C11/4094

CPC classification number: G11C11/4091 ,  G11C11/4094

Abstract: A bitline sense amplifier including: an amplifier which is connected between a first sensing bitline and a second sensing bitline, and detects and amplifies a voltage difference between a first bitline and a second bitline in response to a first control signal and a second control signal; and an equalizer which is connected between a first supply line through which the first control signal is supplied and a second supply line through which the second control signal is supplied, and pre-charges the first bitline and the second bitline with a precharge voltage in response to an equalizing control signal, wherein the equalizer includes an equalizing enable transistor in which a source terminal is connected to the first supply line and performs equalizing in response to the equalizing control signal.

公开(公告)号：US20210391384A1

公开(公告)日：2021-12-16

申请号：US17460635

申请日：2021-08-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Han-Na CHO ,  Bok-Yeon WON ,  Oik KWON

IPC: H01L27/22 ,  H01L43/02 ,  H01L23/528 ,  H01L23/522 ,  H01L43/10

Abstract: A magnetic memory device includes a substrate including a cell region and a peripheral circuit region, lower contact plugs on the cell region, data storage structures on the lower contact plugs, and a peripheral interconnection structure on the peripheral circuit region. The peripheral interconnection structure includes a line portion extending in a direction parallel to a top surface of the substrate, and contact portions extending from the line portion toward the substrate. A height of each of the contact portions is less than a height of each of the lower contact plugs.

公开(公告)号：US20210159272A1

公开(公告)日：2021-05-27

申请号：US16887541

申请日：2020-05-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Han-Na CHO ,  Bok-Yeon WON ,  Oik KWON

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/10 ,  H01L23/522 ,  H01L23/528

Abstract: A magnetic memory device includes a substrate including a cell region and a peripheral circuit region, lower contact plugs on the cell region, data storage structures on the lower contact plugs, and a peripheral interconnection structure on the peripheral circuit region. The peripheral interconnection structure includes a line portion extending in a direction parallel to a top surface of the substrate, and contact portions extending from the line portion toward the substrate. A height of each of the contact portions is less than a height of each of the lower contact plugs.

公开(公告)号：US20180006219A1

公开(公告)日：2018-01-04

申请号：US15414911

申请日：2017-01-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Hun SEO ,  Jung-Ik OH ,  Yoo-Chul KONG ,  Woo-Ram KIM ,  Jong-Chul PARK ,  Gwang-Hyun BAEK ,  Bok-Yeon WON ,  Hye-Jin CHOI

IPC: H01L45/00 ,  H01L27/24 ,  H01L43/12 ,  H01L27/22 ,  H01L43/08 ,  H01L43/02 ,  H01L43/10

CPC classification number: H01L45/1675 ,  H01L27/222 ,  H01L27/2427 ,  H01L27/2463 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L45/06 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147

Abstract: In method of manufacturing a semiconductor memory device, a selection layer and a variable resistance layer may be sequentially formed on a substrate. A preliminary first mask extending in a first direction may be formed on the variable resistance layer. An upper mask extending in a second direction crossing the first direction may be formed on the variable resistance layer and the preliminary first mask. The preliminary first mask may be etched using the upper mask as an etching mask to form a first mask having a pillar shape. The variable resistance layer and the selection layer may be anisotropically etched using the first mask as an etching mask to form a pattern structure including a variable resistance pattern and selection pattern sequentially stacked. The pattern structure may have a pillar shape. Damages to the pattern structure may decrease.

公开(公告)号：US20240386940A1

公开(公告)日：2024-11-21

申请号：US18525276

申请日：2023-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyoungmin KIM ,  Minchae KIM ,  Sujin PARK ,  Bok-Yeon WON ,  Bumjae LEE

IPC: G11C11/408

Abstract: A row decoder includes first and second main wordline driving circuits, which are configured to generate respective first and second driving signals onto corresponding first and second main wordlines extending adjacent to each other. In addition, a first transistor within the first main wordline driving circuit and a second transistor within the second main wordline driving circuit have the same function, but extend in different rows when viewed in a direction perpendicular to a substrate on which the first and second main wordlines are formed.

公开(公告)号：US20240202424A1

公开(公告)日：2024-06-20

申请号：US18335428

申请日：2023-06-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jichang SIM ,  Ohhun KWON ,  Hyuckjoon KWON ,  Bok-Yeon WON

IPC: G06F30/398 ,  G06F30/392

CPC classification number: G06F30/398 ,  G06F30/392

Abstract: A computing device separates a first target layer including a plurality of target patterns from an original design layout, shifts the plurality of target patterns in the first target layer based on misalignment values at positions of the plurality of target patterns to generate a second target layer, and combines the second target layer with the original design layout from which the first target layer is separated to generate a corrected design layout.

公开(公告)号：US20230397438A1

公开(公告)日：2023-12-07

申请号：US18452886

申请日：2023-08-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Han-Na CHO ,  Bok-Yeon WON ,  Oik KWON

IPC: H10B61/00 ,  H01L23/528 ,  H01L23/522 ,  H10N50/80 ,  H10N50/85

CPC classification number: H10B61/22 ,  H01L23/5283 ,  H01L23/5226 ,  H10N50/80 ,  H10N50/85

Abstract: A magnetic memory device includes a substrate including a cell region and a peripheral circuit region, lower contact plugs on the cell region, data storage structures on the lower contact plugs, and a peripheral interconnection structure on the peripheral circuit region. The peripheral interconnection structure includes a line portion extending in a direction parallel to a top surface of the substrate, and contact portions extending from the line portion toward the substrate. A height of each of the contact portions is less than a height of each of the lower contact plugs.

公开(公告)号：US20150016199A1

公开(公告)日：2015-01-15

申请号：US14326543

申请日：2014-07-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bok-Yeon WON ,  Hyuk-Joon KWON

IPC: G11C7/12 ,  H01L27/105

CPC classification number: G11C7/12 ,  G11C11/4094 ,  H01L27/0207 ,  H01L27/10897

Abstract: There is provided a bit line equalizing circuit including: an active region; a first bit line disposed on the active region in a first direction; a second bit line disposed on the active region in the first direction; a gate pattern including a first pattern disposed on the active region in a second direction crossing the first direction, and a second pattern extended from one side of the first pattern to be disposed in the first direction, and formed in a stair shape; a first contact disposed at one side of the first pattern and one side of the second pattern, and configured to connect the active region and the first bit line; a second contact disposed at one side of the first pattern and the other side of the second pattern, and configured to connect the active region and the second bit line; and a third contact disposed at the other side of the first pattern, and configured to provide a predetermined voltage to the active region.

Abstract translation: 提供了一种位线均衡电路，包括：有源区; 在第一方向上设置在有源区上的第一位线; 在所述有源区域上沿所述第一方向设置的第二位线; 形成在第一方向上的第二方向上的第一图案和从第一图案的一侧向第一方向延伸的第二图案，形成为阶梯状; 第一触点，其设置在所述第一图案的一侧和所述第二图案的一侧，并且被配置为连接所述有源区域和所述第一位线; 设置在所述第一图案的一侧和所述第二图案的另一侧的第二触点，并且被配置为连接所述有源区域和所述第二位线; 以及设置在所述第一图案的另一侧的第三触点，并且被配置为向所述有源区域提供预定电压。