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公开(公告)号:US12190995B2
公开(公告)日:2025-01-07
申请号:US18455904
申请日:2023-08-25
Applicant: Samsung Electronics Co., Ltd.
Inventor: Byunghoon Jeong , Kyungtae Kang , Jangwoo Lee , Jeongdon Ihm
IPC: G11C7/22 , G11C7/10 , G11C8/18 , G11C29/42 , H03K19/173
Abstract: A memory device includes a memory cell array configured to store data; and a data output circuit configured to transmit status data to an external device through at least one data line in a latency period in response to a read enable signal received from the external device and transmit the data read from the memory cell array to the external device through the at least one data line in a period subsequent to the latency period.
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公开(公告)号:US11769537B2
公开(公告)日:2023-09-26
申请号:US18069685
申请日:2022-12-21
Applicant: Samsung Electronics Co., Ltd.
Inventor: Byunghoon Jeong , Kyungtae Kang , Jangwoo Lee , Jeongdon Ihm
IPC: G11C7/22 , G11C7/10 , H03K19/173 , G11C8/18 , G11C29/42
CPC classification number: G11C7/222 , G11C7/1057 , G11C7/1063 , G11C7/1084 , G11C8/18 , G11C29/42 , H03K19/1737
Abstract: A memory device includes a memory cell array configured to store data; and a data output circuit configured to transmit status data to an external device through at least one data line in a latency period in response to a read enable signal received from the external device and transmit the data read from the memory cell array to the external device through the at least one data line in a period subsequent to the latency period.
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公开(公告)号:US11107512B2
公开(公告)日:2021-08-31
申请号:US17001941
申请日:2020-08-25
Applicant: Samsung Electronics Co., Ltd.
Inventor: Byunghoon Jeong , Kyungtae Kang , Jangwoo Lee , Jeongdon Ihm
Abstract: A memory device includes a memory cell array configured to store data; and a data output circuit configured to transmit status data to an external device through at least one data line in a latency period in response to a read enable signal received from the external device and transmit the data read from the memory cell array to the external device through the at least one data line in a period subsequent to the latency period.
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公开(公告)号:US10998888B2
公开(公告)日:2021-05-04
申请号:US16861903
申请日:2020-04-29
Applicant: Samsung Electronics Co., Ltd.
Inventor: Dongho Shin , Kyungtae Kang , Junha Lee , Tongsung Kim , Jangwoo Lee , Jeongdon Ihm , Byunghoon Jeong
Abstract: A parameter monitoring circuit includes a code generation circuit configured to generate a first code, to which a first offset is applied, and a second code, to which a second offset is applied; a parameter adjustment circuit configured to generate a first parameter and a second parameter by respectively applying the first code and the second code to a current parameter; a comparator circuit configured to generate a first comparison result and a second comparison result, the first comparison result indicating a comparison result between the first parameter and a reference parameter value, and the second comparison result indicating a comparison result between the second parameter and the reference parameter value; and a parameter error detection circuit configured to detect an error in the current parameter, based on the first comparison result and the second comparison result.
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公开(公告)号:US11562780B2
公开(公告)日:2023-01-24
申请号:US17411421
申请日:2021-08-25
Applicant: Samsung Electronics Co., Ltd.
Inventor: Byunghoon Jeong , Kyungtae Kang , Jangwoo Lee , Jeongdon Ihm
IPC: G11C7/22 , G11C7/10 , H03K19/173 , G11C8/18 , G11C29/42
Abstract: A memory device includes a memory cell array configured to store data; and a data output circuit configured to transmit status data to an external device through at least one data line in a latency period in response to a read enable signal received from the external device and transmit the data read from the memory cell array to the external device through the at least one data line in a period subsequent to the latency period.
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公开(公告)号:US11336266B2
公开(公告)日:2022-05-17
申请号:US17222033
申请日:2021-04-05
Applicant: Samsung Electronics Co., Ltd.
Inventor: Dongho Shin , Kyungtae Kang , Junha Lee , Tongsung Kim , Jangwoo Lee , Jeongdon Ihm , Byunghoon Jeong
Abstract: A method of operating a system including a parameter monitoring circuit and a host, includes generating a first parameter applying a first code to a current parameter, wherein a first offset is applied to the first code; generating a first comparison result by comparing the first parameter with a reference parameter value; generating a second parameter applying a second code to the current parameter, wherein a second offset is applied to the second code; generating a second comparison result by comparing the second parameter with the reference parameter value; detecting an error in the current parameter, based on the first comparison result and the second comparison result; and providing a signal based on the error to the host.
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