公开(公告)号：US20130208524A1

公开(公告)日：2013-08-15

申请号：US13766933

申请日：2013-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： MYUNG-HEE SUNG ,  Chang-Woo Ko ,  Jea-Eun Lee ,  Young-Ho Lee

IPC: G11C5/06

CPC classification number: G11C5/06 ,  G11C5/04 ,  G11C7/02 ,  G11C7/1057 ,  G11C7/1084 ,  G11C7/222 ,  G11C7/225 ,  G11C11/4076 ,  G11C11/4093

Abstract: A memory module includes a plurality of buses. A plurality of memory chips is mounted on a module board and is connected to a first node, a second node, and a plurality of third nodes of the plurality of buses. The first node, the second node, and the third nodes branch off to a first memory chip, a second memory chip, and the third memory chips, respectively. A length of the plurality of buses between the first and second nodes is longer than a length of the plurality of buses between adjacent nodes from among the second node and the third nodes.

Abstract translation: 存储器模块包括多个总线。 多个存储器芯片安装在模块板上并连接到多个总线中的第一节点，第二节点和多个第三节点。 第一节点，第二节点和第三节点分别分支到第一存储器芯片，第二存储器芯片和第三存储器芯片。 第一和第二节点之间的多个总线的长度比第二节点和第三节点之间的相邻节点之间的多个总线的长度长。