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    Memory module and manufacturing method thereof
    2.
    发明授权
    Memory module and manufacturing method thereof 有权
    内存模块及其制造方法

    公开(公告)号：US09406369B2

    公开(公告)日：2016-08-02

    申请号：US14325867

    申请日：2014-07-08

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jong-Hyun Seok ,  Dohyung Kim ,  Kwangseop Kim ,  Young-Ho Lee

    IPC: H01L23/34 ,  G11C11/401 ,  G11C5/02 ,  G11C5/04

    CPC classification number: G11C11/401 ,  G11C5/025 ,  G11C5/04

    Abstract: A memory module includes a printed circuit board; first memory chips disposed in parallel with a long axis of the printed circuit board along a first column; second memory chips disposed in parallel with the long axis of the printed circuit board along a second column; and passive elements disposed between the first memory chips and the second memory chips, wherein the passive elements are connected between input/output pins of each of the first and second memory chips and tap pins.

    Abstract translation: 存储模块包括印刷电路板; 第一存储器芯片，沿着第一列与印刷电路板的长轴平行设置; 第二存储器芯片沿着第二列与印刷电路板的长轴平行布置; 以及设置在所述第一存储器芯片和所述第二存储器芯片之间的无源元件，其中所述无源元件连接在所述第一存储器芯片和所述第二存储器芯片中的每一个的输入/输出引脚之间。

    Method of forming patterns for semiconductor device
    3.
    发明授权
    Method of forming patterns for semiconductor device 有权
    形成半导体器件图案的方法

    公开(公告)号：US09099470B2

    公开(公告)日：2015-08-04

    申请号：US14208456

    申请日：2014-03-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Young-Ho Lee ,  Jae-Hwang Sim ,  Sang-Yong Park ,  Kyung-Lyul Moon

    IPC: H01L21/033 ,  H01L23/528 ,  H01L21/308 ,  H01L21/311 ,  H01L21/762 ,  H01L27/115 ,  H01L21/768 ,  H01L27/108

    CPC classification number: H01L23/528 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76229 ,  H01L21/76816 ,  H01L21/76838 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/11519 ,  H01L27/11526 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Provided is a method of forming patterns for a semiconductor device in which fine patterns and large-width patterns are formed simultaneously and adjacent to each other. In the method, a first layer is formed on a substrate so as to cover a first region and a second region which are included in the substrate. Both a blocking pattern covering a portion of the first layer in the first region and a low-density large-width pattern covering a portion of the first layer in the second region are simultaneously formed. A plurality of sacrificial mask patterns are formed on the first layer and the blocking pattern in the first region. A plurality of spacers covering exposed sidewalls of the plurality of sacrificial mask patterns are formed. The plurality of sacrificial mask patterns are removed. The first layer in the first and second regions are simultaneously etched by using the plurality of spacers and the blocking pattern as etch masks in the first region and using the low-density large-width pattern as an etch mask in the second region.

    Abstract translation: 提供一种形成半导体器件的图案的方法，其中精细图案和大幅图案同时并且彼此相邻地形成。 在该方法中，在衬底上形成第一层以覆盖包括在衬底中的第一区域和第二区域。 同时形成覆盖第一区域中的第一层的一部分的阻挡图案和覆盖第二区域中的第一层的一部分的低密度大图案。 在第一层上形成多个牺牲掩模图案，并在第一区域中形成阻挡图案。 形成覆盖多个牺牲掩模图案的暴露侧壁的多个间隔物。 去除多个牺牲掩模图案。 通过使用多个间隔物和阻挡图案作为第一区域中的蚀刻掩模并且在第二区域中使用低密度大宽度图案作为蚀刻掩模，同时蚀刻第一和第二区域中的第一层。

    Semiconductor devices having fine patterns
    4.
    发明授权
    Semiconductor devices having fine patterns 有权
    具有精细图案的半导体器件

    公开(公告)号：US09093454B2

    公开(公告)日：2015-07-28

    申请号：US14186617

    申请日：2014-02-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sang-Yong Park ,  Jae-Hwang Sim ,  Young-Ho Lee ,  Kyung-Lyul Moon ,  Jae-Kwan Park

    IPC: H01L23/48 ,  H01L23/52 ,  H01L23/528 ,  H01L21/033 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/115

    CPC classification number: H01L23/528 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L21/76838 ,  H01L21/823456 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: In a method of forming a semiconductor device, a feature layer is provided on a substrate and a mask layer is provided on the feature layer. A portion of the mask layer is removed in a first region of the semiconductor device where fine features of the feature layer are to be located, the mask layer remaining in a second region of the semiconductor device where broad features of the feature layer are to be located. A mold mask pattern is provided on the feature layer in the first region and on the mask layer in the second region. A spacer layer is provided on the mold mask pattern in the first region and in the second region. An etching process is performed to etch the spacer layer so that spacers remain at sidewalls of pattern features of the mold mask pattern, and to etch the mask layer in the second region to provide mask layer patterns in the second region. The feature layer is etched using the mask layer patterns as an etch mask in the second region and using the spacers as an etch mask in the first region to provide a feature layer pattern having fine features in the first region and broad features in the second region.

    Abstract translation: 在形成半导体器件的方法中，在衬底上提供特征层，并且在特征层上设置掩模层。 掩模层的一部分在半导体器件的第一区域被去除，其中特征层的精细特征将被定位，掩模层保留在半导体器件的第二区域中，其中特征层的广泛特征将是 位于。 模具掩模图案设置在第一区域中的特征层和第二区域中的掩模层上。 间隔层设置在第一区域和第二区域中的模具掩模图案上。 执行蚀刻工艺以蚀刻间隔层，使得间隔物保留在模具掩模图案的图案特征的侧壁处，并且蚀刻第二区域中的掩模层以在第二区域中提供掩模层图案。 使用掩模层图案作为第二区域中的蚀刻掩模蚀刻特征层，并且在第一区域中使用间隔物作为蚀刻掩模来提供在第一区域中具有精细特征的特征层图案，并且在第二区域中具有广泛特征 。

    Memory module for high-speed operations
    8.
    发明授权
    Memory module for high-speed operations 有权
    内存模块，用于高速运行

    公开(公告)号：US09082464B2

    公开(公告)日：2015-07-14

    申请号：US13766933

    申请日：2013-02-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Myung-Hee Sung ,  Chang-Woo Ko ,  Jea-Eun Lee ,  Young-Ho Lee

    IPC: G11C5/06 ,  G11C5/04 ,  G11C7/02 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4093

    CPC classification number: G11C5/06 ,  G11C5/04 ,  G11C7/02 ,  G11C7/1057 ,  G11C7/1084 ,  G11C7/222 ,  G11C7/225 ,  G11C11/4076 ,  G11C11/4093

    Abstract: A memory module includes a plurality of buses. A plurality of memory chips is mounted on a module board and is connected to a first node, a second node, and a plurality of third nodes of the plurality of buses. The first node, the second node, and the third nodes branch off to a first memory chip, a second memory chip, and the third memory chips, respectively. A length of the plurality of buses between the first and second nodes is longer than a length of the plurality of buses between adjacent nodes from among the second node and the third nodes.

    Abstract translation: 存储器模块包括多个总线。 多个存储器芯片安装在模块板上并连接到多个总线中的第一节点，第二节点和多个第三节点。 第一节点，第二节点和第三节点分别分支到第一存储器芯片，第二存储器芯片和第三存储器芯片。 第一和第二节点之间的多个总线的长度比第二节点和第三节点之间的相邻节点之间的多个总线的长度长。

    MEMORY MODULE FOR HIGH-SPEED OPERATIONS
    10.
    发明申请
    MEMORY MODULE FOR HIGH-SPEED OPERATIONS 有权
    用于高速操作的存储模块

    公开(公告)号：US20130208524A1

    公开(公告)日：2013-08-15

    申请号：US13766933

    申请日：2013-02-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： MYUNG-HEE SUNG ,  Chang-Woo Ko ,  Jea-Eun Lee ,  Young-Ho Lee

    IPC: G11C5/06

    CPC classification number: G11C5/06 ,  G11C5/04 ,  G11C7/02 ,  G11C7/1057 ,  G11C7/1084 ,  G11C7/222 ,  G11C7/225 ,  G11C11/4076 ,  G11C11/4093

    Abstract: A memory module includes a plurality of buses. A plurality of memory chips is mounted on a module board and is connected to a first node, a second node, and a plurality of third nodes of the plurality of buses. The first node, the second node, and the third nodes branch off to a first memory chip, a second memory chip, and the third memory chips, respectively. A length of the plurality of buses between the first and second nodes is longer than a length of the plurality of buses between adjacent nodes from among the second node and the third nodes.

    Abstract translation: 存储器模块包括多个总线。 多个存储器芯片安装在模块板上并连接到多个总线中的第一节点，第二节点和多个第三节点。 第一节点，第二节点和第三节点分别分支到第一存储器芯片，第二存储器芯片和第三存储器芯片。 第一和第二节点之间的多个总线的长度比第二节点和第三节点之间的相邻节点之间的多个总线的长度长。

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