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公开(公告)号：US08832638B2
公开(公告)日：2014-09-09
申请号：US13780891
申请日：2013-02-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jae-Hoon Jeong , Chang-Woo Ko , Ki-Jae Song , Hun-Kyo Seo
CPC classification number: G01R1/0408 , G01R31/2808 , G06F17/5068 , G11C29/56 , G11C2029/5602
Abstract: In a method of designing a printed circuit board, a package capacitance, a package inductance, and a chip capacitance of an actual memory device are calculated. A signal line capacitance and a signal line inductance per unit length of a signal line are calculated based on characteristics of the printed circuit board. A length of the signal line for each pin is determined based on the package capacitance and the signal line capacitance.
Abstract translation: 在设计印刷电路板的方法中，计算实际存储器件的封装电容，封装电感和芯片电容。 基于印刷电路板的特性来计算信号线的每单位长度的信号线电容和信号线电感。 基于封装电容和信号线电容确定每个引脚的信号线的长度。
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公开(公告)号：US09082464B2
公开(公告)日：2015-07-14
申请号：US13766933
申请日：2013-02-14
Applicant: Samsung Electronics Co., Ltd.
Inventor： Myung-Hee Sung , Chang-Woo Ko , Jea-Eun Lee , Young-Ho Lee
IPC: G11C5/06 , G11C5/04 , G11C7/02 , G11C7/10 , G11C7/22 , G11C11/4076 , G11C11/4093
CPC classification number: G11C5/06 , G11C5/04 , G11C7/02 , G11C7/1057 , G11C7/1084 , G11C7/222 , G11C7/225 , G11C11/4076 , G11C11/4093
Abstract: A memory module includes a plurality of buses. A plurality of memory chips is mounted on a module board and is connected to a first node, a second node, and a plurality of third nodes of the plurality of buses. The first node, the second node, and the third nodes branch off to a first memory chip, a second memory chip, and the third memory chips, respectively. A length of the plurality of buses between the first and second nodes is longer than a length of the plurality of buses between adjacent nodes from among the second node and the third nodes.
Abstract translation: 存储器模块包括多个总线。 多个存储器芯片安装在模块板上并连接到多个总线中的第一节点，第二节点和多个第三节点。 第一节点，第二节点和第三节点分别分支到第一存储器芯片，第二存储器芯片和第三存储器芯片。 第一和第二节点之间的多个总线的长度比第二节点和第三节点之间的相邻节点之间的多个总线的长度长。
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公开(公告)号：US20130208524A1
公开(公告)日：2013-08-15
申请号：US13766933
申请日：2013-02-14
Applicant: Samsung Electronics Co., Ltd.
Inventor： MYUNG-HEE SUNG , Chang-Woo Ko , Jea-Eun Lee , Young-Ho Lee
IPC: G11C5/06
CPC classification number: G11C5/06 , G11C5/04 , G11C7/02 , G11C7/1057 , G11C7/1084 , G11C7/222 , G11C7/225 , G11C11/4076 , G11C11/4093
Abstract: A memory module includes a plurality of buses. A plurality of memory chips is mounted on a module board and is connected to a first node, a second node, and a plurality of third nodes of the plurality of buses. The first node, the second node, and the third nodes branch off to a first memory chip, a second memory chip, and the third memory chips, respectively. A length of the plurality of buses between the first and second nodes is longer than a length of the plurality of buses between adjacent nodes from among the second node and the third nodes.
Abstract translation: 存储器模块包括多个总线。 多个存储器芯片安装在模块板上并连接到多个总线中的第一节点，第二节点和多个第三节点。 第一节点，第二节点和第三节点分别分支到第一存储器芯片，第二存储器芯片和第三存储器芯片。 第一和第二节点之间的多个总线的长度比第二节点和第三节点之间的相邻节点之间的多个总线的长度长。
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公开(公告)号：US20130176045A1
公开(公告)日：2013-07-11
申请号：US13780891
申请日：2013-02-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jae-Hoon Jeong , Chang-Woo Ko , Ki-Jae Song , Hun-Kyo Seo
IPC: G01R1/04
CPC classification number: G01R1/0408 , G01R31/2808 , G06F17/5068 , G11C29/56 , G11C2029/5602
Abstract: In a method of designing a printed circuit board, a package capacitance, a package inductance, and a chip capacitance of an actual memory device are calculated. A signal line capacitance and a signal line inductance per unit length of a signal line are calculated based on characteristics of the printed circuit board. A length of the signal line for each pin is determined based on the package capacitance and the signal line capacitance.
Abstract translation: 在设计印刷电路板的方法中，计算实际存储器件的封装电容，封装电感和芯片电容。 基于印刷电路板的特性来计算信号线的每单位长度的信号线电容和信号线电感。 基于封装电容和信号线电容确定每个引脚的信号线的长度。
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