公开(公告)号：US20240339536A1

公开(公告)日：2024-10-10

申请号：US18478215

申请日：2023-09-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin Young CHOI ,  Woo Sung PARK ,  Min Seok JO ,  Ji Won PARK ,  Han Young SONG

IPC: H01L29/78 ,  H01L21/8234 ,  H01L23/48 ,  H01L23/528 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/481 ,  H01L23/528 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes a back interlayer insulating film, a back wiring line in the back interlayer insulating film, a fin-shaped pattern on a first surface of the back wiring line, a field insulating film disposed on the fin-shaped pattern, a source/drain pattern on the fin-shaped pattern, a source/drain contact disposed on the source/drain pattern and connected to the source/drain pattern and a contact connecting via connecting the back wiring line and the source/drain contact, and is in contact with the back wiring line. The contact connecting via includes a first surface connected to the source/drain contact, and a second surface contacted to the back wiring line. A height from a second surface of the back wiring line to an upper surface of the field insulating film is smaller than a height from the second surface of the back wiring line to the first surface of the contact connecting via.

公开(公告)号：US20190305099A1

公开(公告)日：2019-10-03

申请号：US16178159

申请日：2018-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min Seok JO ,  Jae Hyun LEE ,  Jong Han LEE ,  Hong Bae PARK

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/762

Abstract: A semiconductor device includes a first fin type pattern and a second fin type pattern, which are isolated from each other by an isolating trench, and extend in a first direction on a substrate, respectively, a third fin type pattern which is spaced apart from the first fin type pattern and the second fin type pattern in a second direction and extends in the first direction, a field insulation film on a part of sidewalls of the first to third fin type patterns, a device isolation structure, which extends in the second direction, and is in the isolating trench, a gate insulation support, which extends in the first direction on the field insulation film between the first fin type pattern and the third fin type pattern, a gate structure, which intersects the third fin type pattern, extends in the second direction, and is in contact with the gate insulation support, wherein a height from the substrate to a bottom surface of the gate structure is greater than a height from the substrate to a bottom surface of the gate insulation support.