公开(公告)号：US09390784B2

公开(公告)日：2016-07-12

申请号：US14290088

申请日：2014-05-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min-hee Cho ,  Satoru Yamada ,  Sang-ho Shin ,  Sung-sam Lee

IPC: G11C11/406 ,  G11C7/04 ,  G11C16/34

CPC classification number: G11C11/40626 ,  G11C7/04 ,  G11C16/3418 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A semiconductor memory device includes: a memory unit including a first memory sub region including a first memory cell and a second memory sub region including a second memory cell; a temperature information obtaining unit that obtains temperature information; a temperature estimation unit that estimates a first temperature of the first memory sub region and a second temperature of the second memory sub region based on the temperature information; a first sub region control unit that controls the first memory sub region based on the first temperature; and a second sub region control unit that controls the second memory sub region based on the second temperature.

Abstract translation: 半导体存储器件包括：存储单元，包括包括第一存储单元的第一存储器子区域和包括第二存储器单元的第二存储器子区域; 获取温度信息的温度信息获取单元; 温度估计单元，其基于所述温度信息来估计所述第一存储器子区域的第一温度和所述第二存储器子区域的第二温度; 第一子区域控制单元，其基于第一温度来控制第一存储器子区域; 以及第二子区域控制单元，其基于第二温度来控制第二存储器子区域。

公开(公告)号：US10896951B2

公开(公告)日：2021-01-19

申请号：US16545906

申请日：2019-08-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woo-bin Song ,  Hei-seung Kim ,  Mirco Cantoro ,  Sang-woo Lee ,  Min-hee Cho ,  Beom-yong Hwang

IPC: H01L29/06 ,  H01L29/786 ,  H01L29/22

Abstract: A semiconductor device includes a channel layer located on a substrate, the channel layer including a conductive oxide, a gate structure located on the channel layer, the gate structure including a gate electrode and gate spacers located on both sidewalls of the gate electrode, and source and drain regions located on both sides of the gate structure in recess regions having a first height from a top surface of the channel layer. The source and drain regions are configured to apply tensile stress to a portion of the channel layer located under the gate structure.