公开(公告)号：US20240155833A1

公开(公告)日：2024-05-09

申请号：US18341394

申请日：2023-06-26

申请人： Samsung Electronics Co., Ltd.

发明人： Junhyeok AHN ,  Euna KIM ,  Myeongdong LEE

IPC分类号： H10B12/00

CPC分类号： H10B12/482 ,  H10B12/315 ,  H10B12/488

摘要： A semiconductor device includes a substrate having an active region; word line structures in the substrate and extending in parallel to each other in a first horizontal direction; bit line structures on the substrate and the word line structures and extending in parallel to each other in a second horizontal direction that intersects the first horizontal direction; storage node contacts on a side wall of each of the bit line structures and electrically connected to the active region; and a fence structure having first line pattern portions on the word line structures and extending in the first horizontal direction, second line pattern portions extending in the second horizontal direction, and pillar portions extending from the first line pattern portions between the bit line structures in a vertical direction that is perpendicular to an upper surface of the substrate.

公开(公告)号：US20240315005A1

公开(公告)日：2024-09-19

申请号：US18388266

申请日：2023-11-09

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Kiseok LEE ,  Sangjae PARK ,  Huijung KIM ,  Taejin PARK ,  Chansic YOON ,  Myeongdong LEE

IPC分类号： H10B12/00

CPC分类号： H10B12/315 ,  H10B12/0335 ,  H10B12/482

摘要： A semiconductor device includes an active pattern array including active patterns on a substrate; a first contact structure on a central portion of each active pattern; a bit line structure on the first contact structure; a second contact structure on an end of each active pattern; a third contact structure on the second contact structure; and a capacitor electrically connected to the third contact structure, wherein the active pattern array includes active pattern rows spaced apart from each other in a second direction parallel the substrate, the active pattern rows include active patterns spaced apart from each other in a first direction parallel to the substrate, the active patterns extend in a third direction having an acute angle with the first/second directions, the active patterns in the rows are aligned in the first direction, and the second contact structure has a rectangular shape in a plan view.

公开(公告)号：US20240172426A1

公开(公告)日：2024-05-23

申请号：US18346942

申请日：2023-07-05

申请人： Samsung Electronics Co., Ltd.

发明人： Junhyeok AHN ,  Myeongdong LEE

IPC分类号： H10B12/00

CPC分类号： H10B12/488 ,  H10B12/34

摘要： A semiconductor device may include a device isolation layer on a substrate and defining an active region; and a word line structure in a gate trench defined by the device isolation layer and the active region. The word line structure may include a word line on a gate dielectric layer. The word line may include a second material layer including a doped semiconductor material on a first material layer, may have a first region having a first width and a second region having a second width, which may be wider than the first width. The second material layer may include a first material portion in the first region and a second material portion in the second region. The doped semiconductor material may be a first concentration in the first material portion and a second concentration in the second material portion, which may be lower than the first concentration.

公开(公告)号：US20220344341A1

公开(公告)日：2022-10-27

申请号：US17558855

申请日：2021-12-22

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Huijung KIM ,  Myeongdong LEE ,  Inwoo KIM ,  Sunghee HAN

IPC分类号： H01L27/108 ,  H01L21/768 ,  H01L23/528

摘要： A semiconductor device that includes a substrate including an active region and a contact recess. A gate electrode is disposed in the substrate and extends in a first direction. A bit line structure intersects the gate electrode and extends in a second direction intersecting the first direction. The bit line structure includes a direct contact disposed in the contact recess. A buried contact is disposed on the substrate and is electrically connected to the active region. A spacer structure is disposed between the bit line structure and the buried contact. The spacer structure includes a buried spacer disposed on a lateral side surface of the direct contact, and an air gap disposed on the buried spacer. The air gap exposes a lateral side surface of the bit line structure.

公开(公告)号：US20240321735A1

公开(公告)日：2024-09-26

申请号：US18601467

申请日：2024-03-11

申请人： Samsung Electronics Co., Ltd.

发明人： Seungbo KO ,  Sujin KANG ,  Jongmin KIM ,  Donghyuk AHN ,  Jiwon OH ,  Chansic YOON ,  Myeongdong LEE ,  Minyoung LEE ,  Inho CHA

IPC分类号： H01L23/528 ,  H10B12/00

CPC分类号： H01L23/528 ,  H10B12/00

摘要： A semiconductor device includes a substrate, a word line extending on the substrate in a first horizontal direction, a bit line extending on the substrate in a second horizontal direction perpendicular to the first horizontal direction, and a spacer structure on one sidewall of the bit line, wherein the bit line includes a lower conductive layer, an intermediate conductive layer, and an upper conductive layer stacked in a vertical direction on the substrate, and the spacer structure includes a depletion stopping layer on one sidewall of the lower conductive layer, extending in the vertical direction and including a material layer having an interfacial trap density less than an interfacial trap density of a silicon nitride layer, and an inner spacer extending in the vertical direction and on one sidewall of the depletion stopping layer.

公开(公告)号：US20240315010A1

公开(公告)日：2024-09-19

申请号：US18435198

申请日：2024-02-07

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Taejin PARK ,  Jongmin KIM ,  Huijung KIM ,  Kiseok LEE ,  Myeongdong LEE

IPC分类号： H10B12/00

CPC分类号： H10B12/34 ,  H10B12/03 ,  H10B12/482 ,  H10B12/488

摘要： Provided is a semiconductor device comprising: an active region defined by an element isolation film in a substrate; a word line extending in a first horizontal direction in the substrate; a bit line extending in a second horizontal direction crossing the first horizontal direction on the substrate; an additional pad disposed on the active region; and a buried contact on the additional pad wherein the buried contact is electrically connected to the active region by the additional pad, wherein the additional pad comprises a first surface that overlaps the word line in a vertical direction, and a second surface that is free of overlap with the word line in the vertical direction, and wherein, the first surface meets the second surface at a cusp.