公开(公告)号：US09515150B2

公开(公告)日：2016-12-06

申请号：US14308751

申请日：2014-06-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junjie Xiong ,  Dongho Cha ,  Myung Jin Kang ,  Kihoon Do

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L29/165 ,  H01L21/8238

CPC classification number: H01L29/45 ,  H01L21/02532 ,  H01L21/76805 ,  H01L21/76895 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/41725 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7848

Abstract: Provided are semiconductor devices and methods of manufacturing the same. The methods include providing a substrate including a first region and a second region, forming first mask patterns in the first region, and forming second mask patterns having an etch selectivity with respect to the first mask patterns in the second region. The first mask patterns and the second mask patterns are formed at the same time.

Abstract translation: 提供半导体器件及其制造方法。 所述方法包括提供包括第一区域和第二区域的衬底，在第一区域中形成第一掩模图案，以及形成相对于第二区域中的第一掩模图案具有蚀刻选择性的第二掩模图案。 同时形成第一掩模图案和第二掩模图案。

公开(公告)号：US20150028399A1

公开(公告)日：2015-01-29

申请号：US14308751

申请日：2014-06-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junjie Xiong ,  Dongho Cha ,  Myung Jin Kang ,  Kihoon Do

IPC: H01L29/417

CPC classification number: H01L29/45 ,  H01L21/02532 ,  H01L21/76805 ,  H01L21/76895 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/41725 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7848

Abstract: Provided are semiconductor devices and methods of manufacturing the same. The methods include providing a substrate including a first region and a second region, forming first mask patterns in the first region, and forming second mask patterns having an etch selectivity with respect to the first mask patterns in the second region. The first mask patterns and the second mask patterns are formed at the same time.

Abstract translation: 提供半导体器件及其制造方法。 所述方法包括提供包括第一区域和第二区域的衬底，在第一区域中形成第一掩模图案，以及形成相对于第二区域中的第一掩模图案具有蚀刻选择性的第二掩模图案。 同时形成第一掩模图案和第二掩模图案。

公开(公告)号：US10439033B2

公开(公告)日：2019-10-08

申请号：US15350425

申请日：2016-11-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junjie Xiong ,  Dongho Cha ,  Myung Jin Kang ,  Kihoon Do

IPC: H01L29/45 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L29/165 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/768 ,  H01L27/092 ,  H01L29/08 ,  H01L29/16

Abstract: A semiconductor device can include a substrate with a first source/drain and a second source/drain in the substrate. A first ohmic contact pattern can be in an uppermost surface of the first source/drain, where the first ohmic contact pattern includes a first semiconductor alloyed with a first metal. A second ohmic contact pattern can be in an uppermost surface of the second source/drain, where the second ohmic contact pattern includes a second semiconductor that is different than the first semiconductor and is alloyed with a second metal that is different than the first metal.

公开(公告)号：US20170062579A1

公开(公告)日：2017-03-02

申请号：US15350425

申请日：2016-11-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junjie Xiong ,  Dongho Cha ,  Myung Jin Kang ,  Kihoon Do

IPC: H01L29/45 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L21/02 ,  H01L21/8238 ,  H01L21/285 ,  H01L21/768 ,  H01L21/762 ,  H01L29/66 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L29/45 ,  H01L21/02532 ,  H01L21/76805 ,  H01L21/76895 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/41725 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7848

Abstract: A semiconductor device can include a substrate with a first source/drain and a second source/drain in the substrate. A first ohmic contact pattern can be in an uppermost surface of the first source/drain, where the first ohmic contact pattern includes a first semiconductor alloyed with a first metal. A second ohmic contact pattern can be in an uppermost surface of the second source/drain, where the second ohmic contact pattern includes a second semiconductor that is different than the first semiconductor and is alloyed with a second metal that is different than the first metal.

Abstract translation: 半导体器件可以包括在衬底中具有第一源极/漏极和第二源极/漏极的衬底。 第一欧姆接触图案可以在第一源极/漏极的最上表面中，其中第一欧姆接触图案包括与第一金属合金化的第一半导体。 第二欧姆接触图案可以在第二源极/漏极的最上表面中，其中第二欧姆接触图案包括与第一半导体不同的第二半导体，并且与不同于第一金属的第二金属合金化。

公开(公告)号：US09034719B2

公开(公告)日：2015-05-19

申请号：US14315991

申请日：2014-06-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myung Jin Kang

IPC: H01L21/20 ,  H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1683 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1608

Abstract: A method of forming a variable resistive memory device includes forming a conductive pattern that alternates with a first insulation pattern along a first direction on a substrate that is parallel with a surface of the substrate, forming a preliminary sacrificial pattern on the conductive pattern that contacts a sidewall of the first insulation pattern, etching the conductive pattern using the preliminary sacrificial pattern as an etch masks to form a preliminary bottom electrode pattern, patterning the preliminary sacrificial pattern and the preliminary bottom electrode pattern to form a sacrificial pattern and a bottom electrode pattern that each include at least two portions which are separated from each other along a second direction intersecting the first direction, and replacing the sacrificial pattern with a variable resistive pattern.

Abstract translation: 一种形成可变电阻式存储器件的方法包括：在与衬底的表面平行的衬底上沿第一方向形成与第一绝缘图案交替的导电图案，在与衬底的表面平行的衬底上形成初步牺牲图案， 第一绝缘图案的侧壁，使用预备牺牲图案蚀刻导电图案作为蚀刻掩模以形成初步底部电极图案，图案化初步牺牲图案和预备底部电极图案以形成牺牲图案和底部电极图案， 每个包括沿着与第一方向相交的第二方向彼此分离的至少两个部分，并且以可变电阻图案替换牺牲图案。

公开(公告)号：US08765521B2

公开(公告)日：2014-07-01

申请号：US14143760

申请日：2013-12-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myung Jin Kang ,  Youngnam Hwang

IPC: H01L29/02

CPC classification number: H01L45/1683 ,  H01L27/2409 ,  H01L45/06

Abstract: According to example embodiments, a variable resistance memory device include an ohmic pattern on a substrate; a first electrode pattern including a first portion that has a plate shape and contacts a top surface of the ohmic pattern and a second portion that extends from one end of the first portion to a top; a variable resistance pattern electrically connected to the first electrode pattern; and a second electrode pattern electrically connected to the variable resistance pattern, wherein one end of the ohmic pattern and the other end of the first portion are disposed on the same plane.