公开(公告)号：US20240055338A1

公开(公告)日：2024-02-15

申请号：US18218885

申请日：2023-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byungho KIM ,  Youngchan KO ,  Gyeongho KIM ,  Yongkoon LEE ,  Myungdo CHO ,  Sangseok HONG

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/49822 ,  H01L23/3128 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/48 ,  H01L24/32 ,  H01L24/08 ,  H01L2924/15174 ,  H01L2924/13091 ,  H01L2924/01029 ,  H01L2924/01022 ,  H01L2224/16165 ,  H01L2224/16055 ,  H01L2224/48108 ,  H01L2224/48145 ,  H01L2224/32054 ,  H01L2224/32146 ,  H01L2224/32235 ,  H01L2224/08135

Abstract: A fan-out semiconductor package includes a wiring substrate including a first fan-in region, a fan-out region surrounding the first fan-in region, and a second fan-in region, a first fan-in chip structure, a second fan-in chip structure, a first redistribution structure including first redistribution elements disposed on a bottom surface of the wiring substrate, and a second redistribution structure disposed on a top surface of the wiring substrate, and a chip wiring structure formed on a top surface of the second chip, and the second redistribution structure includes a second redistribution layer extending to the first fan-in region and the fan-out region, a plurality of second redistribution vias integrally formed with the second redistribution layer and extending downward, and a seed layer surrounding the second redistribution layer and bottom surfaces of the plurality of second redistribution vias.

公开(公告)号：US20240421034A1

公开(公告)日：2024-12-19

申请号：US18403936

申请日：2024-01-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byungho KIM ,  Youngchan KO ,  Gyeongho KIM ,  Yongkoon LEE ,  Myungdo CHO

IPC: H01L23/42 ,  H01L23/15 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065

Abstract: A semiconductor package includes: a first redistribution structure including a first insulating layer and first conductive patterns; a connection substrate on the first redistribution structure, and including a base layer and a through electrode penetrating the base layer, wherein the base layer includes a first material; a molding layer at least partially surrounding the connection substrate and disposed on the first redistribution structure, wherein the molding layer includes a second material; a second redistribution structure disposed on the molding layer and the connection substrate; and a plurality of semiconductor devices spaced apart from each other on the second redistribution structure, wherein a first thermal expansion coefficient of the first material of the base layer is less than a second thermal expansion coefficient of the second material of the molding layer, and wherein an upper surface of the base layer is substantially coplanar with an upper surface of the molding layer.