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公开(公告)号：US20240243080A1
公开(公告)日：2024-07-18
申请号：US18307165
申请日：2023-04-26
CPC分类号： H01L24/05 , H01L22/14 , H01L24/03 , H01L24/08 , H01L2224/02215 , H01L2224/03019 , H01L2224/08135
摘要： Various embodiments of the present disclosure are directed towards a semiconductor structure (e.g., an integrated circuit (IC) die) comprising an enhanced cap layer for pad oxidation prevention, as well as a method for forming the IC die. An interconnect pad overlies a substrate at a top of an interconnect structure, and a bond structure overlies and extends from a surface of the interconnect pad. A cap layer and an etch stop layer overlie the surface around the bond structure. Further, the cap layer separates the etch stop layer from the interconnect pad and is soft. Soft may for example, refer to a hardness less than silicon nitride and/or less than the etch stop layer. Because the cap layer is soft, a probe may be pushed through the cap layer to the interconnect pad for testing without first forming a pad opening exposing the interconnect pad.
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公开(公告)号：US11756842B2
公开(公告)日：2023-09-12
申请号：US17448002
申请日：2021-09-17
发明人： Chun-Liang Lu , Chun-Wei Chia , Chun-Hao Chou , Kuo-Cheng Lee
CPC分类号： H01L22/34 , H01L23/585 , H01L24/08 , H01L24/80 , H01L2224/08135 , H01L2224/80895
摘要： A semiconductor device includes a first wafer and a second wafer. The semiconductor device includes a seal ring structure comprising a first metal structure in a body of the first wafer, a second metal structure in the body of the first wafer, a third metal structure in a body of the second wafer, and a metal bonding structure including a first set of metal elements coupling the first metal structure and the third metal structure through an interface between the first wafer and the second wafer, and a second set of metal elements coupling the second metal structure and the third metal structure through the interface between the first wafer and the second wafer.
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公开(公告)号：US20240312937A1
公开(公告)日：2024-09-19
申请号：US18671649
申请日：2024-05-22
发明人： Sung-Min Hwang , Jiwon Kim , Jaeho Ahn , Joon-Sung Lim , Sukkang Sung
IPC分类号： H01L23/00 , G11C16/08 , G11C16/10 , H01L25/00 , H01L25/065 , H01L25/18 , H10B41/27 , H10B41/41 , H10B43/27 , H10B43/40
CPC分类号： H01L24/08 , G11C16/08 , G11C16/10 , H01L24/80 , H01L25/0657 , H01L25/18 , H01L25/50 , H10B41/27 , H10B41/41 , H10B43/27 , H10B43/40 , H01L2224/08135 , H01L2224/80895 , H01L2224/80896 , H01L2924/1431 , H01L2924/14511
摘要： A semiconductor device and electronic system, the device including a cell structure stacked on a peripheral circuit structure, wherein the cell structure includes a first interlayer dielectric layer and first metal pads exposed at the first interlayer dielectric layer and connected to gate electrode layers and channel regions, the peripheral circuit structure includes a second interlayer dielectric layer and second metal pads exposed at the second interlayer dielectric layer and connected to a transistor, the first metal pads include adjacent first and second sub-pads, the second metal pads include adjacent third and fourth sub-pads, the first and third sub-pads are coupled, and a width of the first sub-pad is greater than that of the third sub-pad, and the second sub-pad and the fourth sub-pad are coupled, and a width of the fourth sub-pad is greater than that of the second sub-pad.
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公开(公告)号：US20240105619A1
公开(公告)日：2024-03-28
申请号：US18523553
申请日：2023-11-29
发明人： Fong-Yuan Chang , Noor Mohamed Ettuveettil , Po-Hsiang Huang , Sen-Bor Jan , Ming-Fa Chen , Chin-Chou Liu , Yi-Kan Cheng
IPC分类号： H01L23/528 , H01L23/00 , H01L23/522
CPC分类号： H01L23/5286 , H01L23/5226 , H01L24/09 , H01L2224/08135 , H01L2224/08137 , H01L2224/08145 , H01L2224/08146 , H01L2224/08147
摘要： Semiconductor devices and methods of manufacture are provided wherein a metallization layer is located over a substrate, and a power grid line is located within the metallization layer. A signal pad is located within the metallization layer and the signal pad is surrounded by the power grid line. A signal external connection is electrically connected to the signal pad.
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公开(公告)号：US20170160472A1
公开(公告)日：2017-06-08
申请号：US15436934
申请日：2017-02-20
CPC分类号： G02B6/4228 , G02B6/1221 , G02B6/4231 , G02B6/4257 , G02B2006/12147 , H01L21/6838 , H01L2224/08135 , H01L2224/08145 , H01L2224/08147 , H01L2224/08148 , H01L2224/08221 , H01L2224/08237 , H01L2224/08238 , H01L2224/81141 , H01L2224/81898
摘要： A chip packaging includes a first part comprising a support; and a core polymer layer transversally structured so as to exhibit distinct residual portions comprising: first waveguide cores each having a first height and disposed within said inner region; and one or more first alignment structures disposed within said outer region. A second part of the packaging comprises: second waveguide cores, each having a same second height; and one or more second alignment structures complementarily shaped with respect to the one or more first alignment structures, and wherein, the first part structured such that said inner region is recessed with respect to the outer region, to enable: the second waveguide cores to contact the first waveguide cores; and the one or more second alignment structures to respectively receive, at least partly, the one or more first alignment structures. The invention is further directed to related passive alignment methods.
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公开(公告)号：US20240055338A1
公开(公告)日：2024-02-15
申请号：US18218885
申请日：2023-07-06
发明人： Byungho KIM , Youngchan KO , Gyeongho KIM , Yongkoon LEE , Myungdo CHO , Sangseok HONG
IPC分类号： H01L23/498 , H01L23/31 , H01L23/00
CPC分类号： H01L23/49822 , H01L23/3128 , H01L23/49827 , H01L24/16 , H01L24/48 , H01L24/32 , H01L24/08 , H01L2924/15174 , H01L2924/13091 , H01L2924/01029 , H01L2924/01022 , H01L2224/16165 , H01L2224/16055 , H01L2224/48108 , H01L2224/48145 , H01L2224/32054 , H01L2224/32146 , H01L2224/32235 , H01L2224/08135
摘要： A fan-out semiconductor package includes a wiring substrate including a first fan-in region, a fan-out region surrounding the first fan-in region, and a second fan-in region, a first fan-in chip structure, a second fan-in chip structure, a first redistribution structure including first redistribution elements disposed on a bottom surface of the wiring substrate, and a second redistribution structure disposed on a top surface of the wiring substrate, and a chip wiring structure formed on a top surface of the second chip, and the second redistribution structure includes a second redistribution layer extending to the first fan-in region and the fan-out region, a plurality of second redistribution vias integrally formed with the second redistribution layer and extending downward, and a seed layer surrounding the second redistribution layer and bottom surfaces of the plurality of second redistribution vias.
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公开(公告)号：US09698080B2
公开(公告)日：2017-07-04
申请号：US14846561
申请日：2015-09-04
IPC分类号： H01L23/48 , H01L21/768 , H01L25/065 , H01L25/00 , H01L21/306 , H01L23/00
CPC分类号： H01L23/481 , H01L21/30604 , H01L21/76898 , H01L24/03 , H01L24/09 , H01L24/48 , H01L24/89 , H01L25/0657 , H01L25/50 , H01L2224/031 , H01L2224/0331 , H01L2224/0355 , H01L2224/05553 , H01L2224/08113 , H01L2224/08135 , H01L2224/48091 , H01L2225/06513 , H01L2225/06524 , H01L2225/06527 , H01L2225/06541 , H01L2225/06544 , H01L2225/06548 , H01L2924/00014 , H01L2924/14 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A three-dimensional semiconductor device using redundant bonding-conductor structures to make inter-level electrical connections between multiple semiconductor chips is disclosed. A first chip, or other semiconductor substrate, forms a first active area on its upper surface, and a second chip or other semiconductor substrate forms a second active area on its upper surface. According to the present invention, when the second chip has been mounted above the first chip, either face-up or face-down, the first active area is coupled to the second active area by at least one redundant bonding-conductor structure. In one embodiment, each redundant bonding-conductor structure includes at least one via portion that extends completely through the second chip to perform this function. In another, the redundant bonding-conductor structure extends downward to the top level interconnect. The present invention also includes a method for making such a device.
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8.发明授权Semiconductor device, imaging device and semiconductor device manufacturing method 有权半导体器件，成像器件和半导体器件制造方法公开(公告)号：US09343498B2
公开(公告)日：2016-05-17
申请号：US14734240
申请日：2015-06-09
申请人： OLYMPUS CORPORATION
发明人： Haruhisa Saito
IPC分类号： H01L21/78 , H01L23/00 , H01L25/00 , H01L27/146 , H01L25/065 , H01L23/48 , H01L21/48 , H01L21/50
CPC分类号： H01L27/14634 , H01L21/48 , H01L21/50 , H01L21/78 , H01L23/48 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/89 , H01L24/92 , H01L24/94 , H01L25/0657 , H01L25/50 , H01L27/14636 , H01L27/1469 , H01L2224/0401 , H01L2224/05568 , H01L2224/05624 , H01L2224/05644 , H01L2224/08112 , H01L2224/08135 , H01L2224/1145 , H01L2224/11452 , H01L2224/1146 , H01L2224/11472 , H01L2224/1148 , H01L2224/1184 , H01L2224/13013 , H01L2224/13017 , H01L2224/13082 , H01L2224/13144 , H01L2224/13155 , H01L2224/1411 , H01L2224/16057 , H01L2224/16106 , H01L2224/27416 , H01L2224/27436 , H01L2224/2919 , H01L2224/73104 , H01L2224/73204 , H01L2224/8012 , H01L2224/81193 , H01L2224/83193 , H01L2224/83194 , H01L2224/83855 , H01L2224/83856 , H01L2224/83862 , H01L2224/9211 , H01L2224/94 , H01L2225/06513 , H01L2924/12042 , H01L2224/83 , H01L2224/81 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： A semiconductor device manufacturing method includes a wafer stack manufacturing process and a dicing process. The wafer stack manufacturing process includes: a first wafer manufacturing process of manufacturing a resin film covering circuits and heated to a temperature higher than a glass transition point of the resin film, manufacturing first holes extending from a surface of the resin film to wirings of the circuits, and providing electrodes electrically connected to the wirings in the first holes to form a first wafer; a second wafer manufacturing process of manufacturing a resin film covering circuits and heated to a temperature lower than a glass transition point of the resin film, manufacturing second holes extending from a surface of the resin film to wirings of the circuits, and providing the electrodes electrically connected to the wirings in the second holes to form a second wafer; and a wafer bonding process.
摘要翻译： 半导体器件制造方法包括晶片堆叠制造工艺和切割工艺。 晶片堆栈制造工艺包括：制造树脂膜覆盖电路并被加热到高于树脂膜的玻璃化转变点的温度的第一晶片制造工艺，制造从树脂膜的表面延伸到第一孔的布线 并且提供与第一孔中的布线电连接以形成第一晶片的电极; 制造树脂膜覆盖电路并被加热到低于树脂膜的玻璃化转变点的温度的第二晶片制造工艺，制造从树脂膜的表面延伸到电路的布线的第二孔，并且将电极提供电 连接到第二孔中的布线以形成第二晶片; 和晶圆接合工艺。
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公开(公告)号：US08134235B2
公开(公告)日：2012-03-13
申请号：US11788974
申请日：2007-04-23
IPC分类号： H01L23/48
CPC分类号： H01L23/481 , H01L21/30604 , H01L21/76898 , H01L24/03 , H01L24/09 , H01L24/48 , H01L24/89 , H01L25/0657 , H01L25/50 , H01L2224/031 , H01L2224/0331 , H01L2224/0355 , H01L2224/05553 , H01L2224/08113 , H01L2224/08135 , H01L2224/48091 , H01L2225/06513 , H01L2225/06524 , H01L2225/06527 , H01L2225/06541 , H01L2225/06544 , H01L2225/06548 , H01L2924/00014 , H01L2924/14 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A three-dimensional semiconductor device using redundant bonding-conductor structures to make inter-level electrical connections between multiple semiconductor chips. A first chip, or other semiconductor substrate, forms a first active area on its upper surface, and a second chip or other semiconductor substrate forms a second active area on its upper surface. According to the present invention, when the second chip has been mounted above the first chip, either face-up or face-down, the first active area is coupled to the second active area by at least one redundant bonding-conductor structure. In one embodiment, each redundant bonding-conductor structure includes at least one via portion that extends completely through the second chip to perform this function. In another, the redundant bonding-conductor structure extends downward to the top level interconnect. The present invention also includes a method for making such a device.
摘要翻译： 一种使用冗余接合导体结构的三维半导体器件，用于在多个半导体芯片之间进行层间电连接。 第一芯片或其它半导体衬底在其上表面上形成第一有源区，并且第二芯片或其它半导体衬底在其上表面上形成第二有源区。 根据本发明，当第二芯片已经被安装在第一芯片上方面向上或向下时，第一有效区域通过至少一个冗余结合导体结构耦合到第二有源区域。 在一个实施例中，每个冗余接合导体结构包括至少一个贯穿第二芯片的至少一个通孔部分，以执行该功能。 另一方面，冗余接合导体结构向下延伸到顶层互连。 本发明还包括制造这种装置的方法。
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公开(公告)号：US12009325B2
公开(公告)日：2024-06-11
申请号：US17328176
申请日：2021-05-24
发明人： Sung-Min Hwang , Jiwon Kim , Jaeho Ahn , Joon-Sung Lim , Sukkang Sung
IPC分类号： H01L23/00 , G11C16/08 , G11C16/10 , H01L25/00 , H01L25/065 , H01L25/18 , H10B41/27 , H10B41/41 , H10B43/27 , H10B43/40
CPC分类号： H01L24/08 , G11C16/08 , G11C16/10 , H01L24/80 , H01L25/0657 , H01L25/18 , H01L25/50 , H10B41/27 , H10B41/41 , H10B43/27 , H10B43/40 , H01L2224/08135 , H01L2224/80895 , H01L2224/80896 , H01L2924/1431 , H01L2924/14511
摘要： A semiconductor device and electronic system, the device including a cell structure stacked on a peripheral circuit structure, wherein the cell structure includes a first interlayer dielectric layer and first metal pads exposed at the first interlayer dielectric layer and connected to gate electrode layers and channel regions, the peripheral circuit structure includes a second interlayer dielectric layer and second metal pads exposed at the second interlayer dielectric layer and connected to a transistor, the first metal pads include adjacent first and second sub-pads, the second metal pads include adjacent third and fourth sub-pads, the first and third sub-pads are coupled, and a width of the first sub-pad is greater than that of the third sub-pad, and the second sub-pad and the fourth sub-pad are coupled, and a width of the fourth sub-pad is greater than that of the second sub-pad.
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