公开(公告)号：US12080637B2

公开(公告)日：2024-09-03

申请号：US17725627

申请日：2022-04-21

申请人： Dai Nippon Printing Co., Ltd.

发明人： Satoru Kuramochi ,  Sumio Koiwa ,  Hidenori Yoshioka

IPC分类号： H01L23/498 ,  H01L23/48 ,  H01L25/065 ,  H01L25/18 ,  H05K1/11 ,  H05K3/28 ,  H05K3/44 ,  H01L23/00 ,  H01L23/13 ,  H01L23/15

CPC分类号： H01L23/49827 ,  H01L23/481 ,  H01L23/49894 ,  H01L25/065 ,  H01L25/18 ,  H05K1/115 ,  H05K3/28 ,  H05K3/445 ,  H01L23/13 ,  H01L23/15 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/13109 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16165 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2224/81805 ,  H01L2224/8385 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2924/14 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/381 ,  H05K2201/09154 ,  H05K2201/09563 ,  H05K2201/09581 ,  H05K2201/0959 ,  H05K2201/09854 ,  H05K2203/0594 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/15788 ,  H01L2924/00014 ,  H01L2924/15787 ,  H01L2924/05432 ,  H01L2924/1579 ,  H01L2924/00014 ,  H01L2224/13109 ,  H01L2924/00014 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2224/13144 ,  H01L2924/00014 ,  H01L2224/81805 ,  H01L2924/00014 ,  H01L2224/8385 ,  H01L2924/00014 ,  H01L2224/2919 ,  H01L2924/0665 ,  H01L2224/2919 ,  H01L2924/07025

摘要： A through-hole electrode substrate includes a substrate including a through-hole extending from a first aperture of a first surface to a second aperture of a second surface, an area of the second aperture being larger than that of the first aperture, the through-hole having a minimum aperture part between the first aperture and the second aperture, wherein an area of the minimum aperture part in a planer view is smallest among a plurality of areas of the through-hole in a planer view, a filler arranged within the through-hole, and at least one gas discharge member contacting the filler exposed to one of the first surface and the second surface.

公开(公告)号：US20240006389A1

公开(公告)日：2024-01-04

申请号：US18343590

申请日：2023-06-28

申请人： CANON KABUSHIKI KAISHA

发明人： HIROAKI KOBAYASHI

IPC分类号： H01L25/16 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00

CPC分类号： H01L25/16 ,  H01L23/49822 ,  H01L23/49872 ,  H01L23/3128 ,  H01L24/16 ,  H01L2224/16165 ,  H01L2924/1205 ,  H01L2924/13067 ,  H01L2924/13091 ,  H01L2924/13069

摘要： Embodiments of the present disclosure provide a technique advantageous to an improvement in performance of a semiconductor device. The semiconductor device includes a first monocrystalline semiconductor layer on which a first semiconductor element is arranged, a second monocrystalline semiconductor layer on which a second semiconductor element is arranged, and a thin film transistor electrically connected to the first semiconductor element without an intervention of another semiconductor element arranged on the first monocrystalline semiconductor layer and electrically connected to the second semiconductor element without an intervention of another semiconductor element arranged on the second monocrystalline semiconductor layer.

公开(公告)号：US09349707B1

公开(公告)日：2016-05-24

申请号：US14609896

申请日：2015-01-30

申请人： Invensas Corporation

发明人： Zhuowen Sun ,  Yong Chen ,  Kyong-Mo Bang

IPC分类号： H01L23/02 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48

CPC分类号： H01L25/0652 ,  H01L21/486 ,  H01L23/13 ,  H01L23/34 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/17 ,  H01L24/43 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L24/85 ,  H01L25/50 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/16057 ,  H01L2224/16137 ,  H01L2224/16146 ,  H01L2224/16165 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/4502 ,  H01L2224/48138 ,  H01L2224/48148 ,  H01L2224/48165 ,  H01L2224/48235 ,  H01L2224/4824 ,  H01L2224/49174 ,  H01L2224/49177 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/1434 ,  H01L2924/1511 ,  H01L2924/152 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/3701 ,  H01L2224/45099

摘要： An apparatus relates generally to a microelectronic assembly. In this apparatus, a first substrate and a second substrate each have opposing surfaces. Contact arrangements are disposed on a surface of the first substrate, including: first contacts disposed as a ring to provide a first array of the contact arrangements on such surface; and second contacts disposed interior to the ring of the first contacts to provide a second array of the contact arrangements on the first surface. The first contacts and the second contacts are for interconnection with first microelectronic dies and second microelectronic dies. The second microelectronic dies are disposed below the first microelectronic dies in same a package as the first microelectronic dies. The first microelectronic dies and the second microelectronic dies include at least two ranks thereof for commonly sharing the first contacts and the second contacts among the first microelectronic dies and the second microelectronic dies.

摘要翻译： 装置一般涉及微电子组件。 在该装置中，第一基板和第二基板各自具有相对的表面。 接触装置设置在第一基板的表面上，包括：作为环设置的第一触点，以在该表面上提供接触装置的第一阵列; 以及第二触点，其设置在第一触头的环的内部，以在第一表面上提供接触装置的第二阵列。 第一触点和第二触点用于与第一微电子管芯和第二微电子管芯互连。 第二微电子管芯以与第一微电子管芯相同的封装设置在第一微电子管芯的下方。 第一微电子管芯和第二微电子管芯包括至少两个等级，用于共同共享第一微触点和第一微电子管芯与第二微电子管芯之间的第二触点。

公开(公告)号：US20140356635A1

公开(公告)日：2014-12-04

申请号：US13967186

申请日：2013-08-14

申请人： QUALCOMM Incorporated

发明人： Chin-Kwan Kim

IPC分类号： H05K1/02 ,  H05K3/44

CPC分类号： H05K1/0271 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/562 ,  H01L2224/131 ,  H01L2224/16165 ,  H01L2224/73253 ,  H01L2924/15311 ,  H01L2924/16251 ,  H01L2924/3511 ,  H05K1/0306 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/068 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/10734 ,  Y10T428/31678 ,  H01L2924/014

摘要： Some novel features pertain to a substrate that includes a first core layer, a second core layer laterally located to the first core layer in the substrate, a first inorganic core layer (e.g., glass, silicon, ceramic) laterally positioned between the first core layer and the second core layer, the first inorganic core layer configured to be vertically aligned with a die configured to be coupled to the substrate, and a dielectric layer covering the first core layer, the second core layer and the first inorganic core layer. In some implementations, the first inorganic core layer has a first coefficient of thermal expansion (CTE), the die has a second coefficient of thermal expansion, and the first core layer has a third coefficient of thermal expansion (CTE). The first CTE of the first inorganic core layer closely matches the second CTE of the die in order to reduce the likelihood of warpage.

摘要翻译： 一些新颖特征涉及一种衬底，其包括第一芯层，横向位于衬底中的第一芯层的第二芯层，侧向位于第一芯层之间的第一无机芯层（例如，玻璃，硅，陶瓷） 和第二芯层，被配置为与被配置为耦合到基板的管芯垂直对准的第一无机芯层，以及覆盖第一芯层，第二芯层和第一无机芯层的电介质层。 在一些实施方案中，第一无机核心层具有第一热膨胀系数（CTE），所述管芯具有第二热膨胀系数，并且所述第一核心层具有第三热膨胀系数（CTE）。 第一无机芯层的第一CTE与模具的第二CTE紧密匹配，以减少翘曲的可能性。

公开(公告)号：US20110304058A1

公开(公告)日：2011-12-15

申请号：US12969451

申请日：2010-12-15

申请人： Rajendra D. Pendse

发明人： Rajendra D. Pendse

IPC分类号： H01L23/488 ,  H01L21/60

CPC分类号： H05K3/3452 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L23/49811 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1134 ,  H01L2224/11825 ,  H01L2224/11849 ,  H01L2224/13017 ,  H01L2224/13019 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13553 ,  H01L2224/13562 ,  H01L2224/14133 ,  H01L2224/16013 ,  H01L2224/16014 ,  H01L2224/16165 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81203 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06558 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30105 ,  H05K3/0005 ,  H05K3/3436 ,  H05K2201/0989 ,  H05K2201/10734 ,  Y02P70/613 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/01082 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552 ,  H01L2224/81805

摘要： A semiconductor device has a semiconductor die having a plurality of bumps formed over a surface of the semiconductor die. The bumps can include a fusible portion and non-fusible portion. Conductive traces are formed over the substrate with interconnect sites having an exposed sidewall and sized according to a design rule defined by SRO+2*SRR−2X, where SRO is an opening over the interconnect site, SRR is a registration for the manufacturing process, and X is a function of a thickness of the exposed sidewall of the contact pad. The bumps are misaligned with the interconnect sites by a maximum distance of X which ranges from 5 to 20 microns. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surface of the interconnect sites. An encapsulant is deposited around the bumps between the semiconductor die and substrate.

摘要翻译： 半导体器件具有在半导体管芯的表面上形成有多个凸点的半导体管芯。 凸块可以包括可熔部分和不可熔部分。 导电迹线形成在衬底上，具有暴露侧壁的互连部位，并且根据由SRO + 2 * SRR-2X定义的设计规则来确定尺寸，其中SRO是互连部位上的开口，SRR是制造过程的注册， 并且X是接触垫的暴露的侧壁的厚度的函数。 这些凸块与互连部位不对准X的最大距离，范围为5至20微米。 这些凸块被结合到互连部位，使得凸块覆盖互连部位的顶表面和侧表面。 围绕半导体管芯和衬底之间的凸块沉积密封剂。

公开(公告)号：US12051649B2

公开(公告)日：2024-07-30

申请号：US18355824

申请日：2023-07-20

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chen-Hua Yu ,  Chieh-Yen Chen ,  Chuei-Tang Wang ,  Chung-Hao Tsai

IPC分类号： H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L25/10

CPC分类号： H01L23/5381 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/81 ,  H01L25/105 ,  H01L2224/16146 ,  H01L2224/16165 ,  H01L2224/818 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/182

摘要： A method includes forming a reconstructed wafer, which includes forming a redistribution structure over a carrier, bonding a first plurality of memory dies over the redistribution structure, bonding a plurality of bridge dies over the redistribution structure, and bonding a plurality of logic dies over the first plurality of memory dies and the plurality of bridge dies. Each of the plurality of bridge dies interconnects, and is overlapped by corner regions of, four of the plurality of logic dies. A second plurality of memory dies are bonded over the plurality of logic dies. The plurality of logic dies form a first array, and the second plurality of memory dies form a second array.

公开(公告)号：US20240047385A1

公开(公告)日：2024-02-08

申请号：US18491637

申请日：2023-10-20

申请人： HUAWEI TECHNOLOGIES CO., LTD.

发明人： Kehan Sui ,  Xinhao Bai ,  Yan Zhou ,  Yuanbin Cai

IPC分类号： H01L23/64 ,  H01L23/00 ,  H01L23/498 ,  H01L23/367 ,  H01L25/065

CPC分类号： H01L23/642 ,  H01L24/16 ,  H01L23/49822 ,  H01L23/3672 ,  H01L24/32 ,  H01L25/0657 ,  H01L23/645 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2224/16165 ,  H01L2224/16146 ,  H01L2224/32146 ,  H01L2224/32235 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1427

摘要： Embodiments of this application provide a filtering structure and an electronic device. In the filtering structure, an intermediate assembly is disposed between a chip and a circuit board, a first filtering assembly is disposed inside the intermediate assembly, and at least a part of a second filtering assembly is disposed on a surface that is of the circuit board and that is away from the intermediate assembly, so that the first filtering assembly is close to the chip. This shortens a filtering path of the chip, improves a dynamic response capability of the chip, and therefore improves an overall filtering capability.

公开(公告)号：US11682613B2

公开(公告)日：2023-06-20

申请号：US17360701

申请日：2021-06-28

申请人： Intel Corporation

发明人： Zhiguo Qian ,  Kaladhar Radhakrishnan ,  Kemal Aygun

IPC分类号： H01L23/49 ,  H01L23/64 ,  H01L23/498 ,  H01L21/68 ,  H01L21/48 ,  H01L23/00 ,  H01L23/538

CPC分类号： H01L23/49816 ,  H01L21/4853 ,  H01L21/68 ,  H01L23/49827 ,  H01L24/17 ,  H01L23/5384 ,  H01L2224/08165 ,  H01L2224/16157 ,  H01L2224/16165 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/24221 ,  H01L2224/32165 ,  H01L2224/32235 ,  H01L2224/73103 ,  H01L2224/73104 ,  H01L2224/73153 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2924/30111

摘要： The present disclosure is directed to systems and methods for improving the impedance matching of semiconductor package substrates by incorporating one or more magnetic build-up layers proximate relatively large diameter, relatively high capacitance, conductive pads formed on the lower surface of the semiconductor package substrate. The one or more magnetic layers may be formed using a magnetic build-up material deposited on the lower surface of the semiconductor package substrate. Vias conductively coupling the conductive pads to bump pads on the upper surface of the semiconductor package substrate pass through and are at least partially surrounded by the magnetic build-up material.

公开(公告)号：US20190172780A1

公开(公告)日：2019-06-06

申请号：US16266203

申请日：2019-02-04

申请人： DAI NIPPON PRINTING CO., LTD.

发明人： Satoru KURAMOCHI ,  Sumio KOIWA ,  Hidenori YOSHIOKA

IPC分类号： H01L23/498 ,  H01L25/18 ,  H05K1/11 ,  H01L23/48 ,  H01L25/065 ,  H05K3/28 ,  H05K3/44

CPC分类号： H01L23/49827 ,  H01L23/13 ,  H01L23/15 ,  H01L23/481 ,  H01L23/49894 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/065 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/13109 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16165 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2224/81805 ,  H01L2224/8385 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2924/14 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/381 ,  H05K1/115 ,  H05K3/28 ,  H05K3/445 ,  H05K2201/09154 ,  H05K2201/09563 ,  H05K2201/09581 ,  H05K2201/0959 ,  H05K2201/09854 ,  H05K2203/0594 ,  H01L2924/00014 ,  H01L2924/05432 ,  H01L2924/0665 ,  H01L2924/07025

摘要： A through-hole electrode substrate includes a substrate including a through-hole extending from a first aperture of a first surface to a second aperture of a second surface, an area of the second aperture being larger than that of the first aperture, the through-hole having a minimum aperture part between the first aperture and the second aperture, wherein an area of the minimum aperture part in a planer view is smallest among a plurality of areas of the through-hole in a planer view, a filler arranged within the through-hole, and at least one gas discharge member contacting the filler exposed to one of the first surface and the second surface.

公开(公告)号：US20190131271A1

公开(公告)日：2019-05-02

申请号：US15856065

申请日：2017-12-28

申请人： Industrial Technology Research Institute ,  Intellectual Property Innovation Corporation

发明人： Shu-Wei Kuo ,  Wei-Yuan Cheng ,  Shau-Fei Cheng

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/544 ,  H01L21/67 ,  H01L21/48

CPC分类号： H01L24/75 ,  H01L21/4853 ,  H01L21/67144 ,  H01L23/3185 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/544 ,  H01L24/16 ,  H01L24/81 ,  H01L2223/54426 ,  H01L2224/16165 ,  H01L2224/75753 ,  H01L2224/75756 ,  H01L2224/81121 ,  H01L2224/81136

摘要： A chip bonding apparatus for bonding a chip and a redistribution structure with each other is provided. The chip bonding apparatus includes a pick and place module and an alignment module. The pick and place module is suitable for picking up and placing the chip. The alignment module is movably connected to the pick and place module. The alignment module includes at least one alignment protrusion, wherein the at least one alignment protrusion extends toward at least one alignment socket included in the redistribution structure. Furthermore, a chip bonding method and a chip package structure are provided.