公开(公告)号：US20190019759A1

公开(公告)日：2019-01-17

申请号：US16135234

申请日：2018-09-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang Hoon AHN ,  Tae Soo KIM ,  Jong Min BAEK ,  Woo Kyung YOU ,  Thomas OSZINDA ,  Byung Hee KIM ,  Nae In LEE

IPC: H01L23/532

Abstract: A semiconductor device includes an element layer, a plurality of first interconnect lines on the element layer, a first insulation layer including carbon having a uniform concentration distribution between the first interconnect lines, a plurality of second interconnect lines spaced from the first interconnect lines, and a second insulation layer between the second interconnect lines. An air spacing is included between the second interconnect lines.

公开(公告)号：US20180102280A1

公开(公告)日：2018-04-12

申请号：US15636889

申请日：2017-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Viet Ha NGUYEN ,  Nae In LEE ,  Thomas OSZINDA ,  Byung Hee KIM ,  Jong Min BAEK ,  Tae Jin YIM

IPC: H01L21/768

CPC classification number: H01L21/76826 ,  H01L21/76814 ,  H01L21/76877 ,  H01L21/76888

Abstract: Methods for fabricating semiconductor devices may provide enhanced performance and reliability by recovering quality of a low-k insulating film damaged by a plasma process. A method may include forming a first interlayer insulating film having a trench therein on a substrate, filling at least a portion of the trench with a metal wiring region, exposing a surface of the metal wiring region and a surface of the first interlayer insulating film to a plasma in a first surface treatment process, then exposing the surface of the first interlayer insulating film to a recovery gas containing a methyl group (—CH3) in a second surface treatment process, and then forming an etch stop layer on the metal wiring region and the first interlayer insulating film.

公开(公告)号：US20190259744A1

公开(公告)日：2019-08-22

申请号：US16400465

申请日：2019-05-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho Jin LEE ,  Seok Ho KIM ,  Kwang Jin MOON ,  Byung Lyul PARK ,  Nae In LEE

IPC: H01L25/00 ,  H01L21/3065 ,  H01L21/768 ,  H01L21/308 ,  H01L23/00 ,  H01L25/065

Abstract: There is provided a method for fabricating a substrate structure capable of enhancing process reproducibility and process stability by trimming a bevel region of a substrate using a wafer level process. The method includes providing a first substrate including first and second surfaces opposite each other and a first device region formed at the first surface, providing a second substrate including third and fourth surfaces opposite each other and a second device region at the third surface, bonding the first substrate and the second substrate to electrically connect the first device region and the second device region, and forming a trimmed substrate. The forming the trimmed substrate includes etching an edge region of the second substrate bonded to the first substrate.

公开(公告)号：US20170213786A1

公开(公告)日：2017-07-27

申请号：US15333508

申请日：2016-10-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Hoon AHN ,  Tae Soo KIM ,  Jong Min BAEK ,  Woo Kyung YOU ,  Thomas OSZINDA ,  Byung Hee KIM ,  Nae In LEE

IPC: H01L23/498 ,  H01L23/535

CPC classification number: H01L23/53295 ,  H01L23/5222 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329

Abstract: A semiconductor device includes an element layer, a plurality of first interconnect lines on the element layer, a first insulation layer including carbon having a uniform concentration distribution between the first interconnect lines, a plurality of second interconnect lines spaced from the first interconnect lines, and a second insulation layer between the second interconnect lines. An air spacing is included between the second interconnect lines.