公开(公告)号：US20250054891A1

公开(公告)日：2025-02-13

申请号：US18928344

申请日：2024-10-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju Bin SEO ,  Seok Ho KIM ,  Kwang Jin MOON

IPC: H01L23/00 ,  H01L21/66 ,  H01L23/498 ,  H01L25/065

Abstract: A semiconductor package that include first and second semiconductor chips bonded together, wherein the first semiconductor chip includes a first semiconductor substrate, a first semiconductor element layer and a first wiring structure sequentially stacked on a first surface of the first semiconductor substrate, first connecting pads and first test pads on the first wiring structure, and first front-side bonding pads, which are connected to the first connecting pads, wherein the second semiconductor chip includes a second semiconductor substrate, a second semiconductor element layer and a second wiring structure sequentially stacked on a third surface of the second semiconductor substrate, and first back-side bonding pads bonded to the first front-side bonding pads on the fourth surface of the second semiconductor substrate, and wherein the first test pads are not electrically connected to the second semiconductor chip.

公开(公告)号：US20240339420A1

公开(公告)日：2024-10-10

申请号：US18537960

申请日：2023-12-13

Applicant: SAMSUNG ELECTRONICS CO, LTD.

Inventor： JU BIN SEO ,  Seok Ho KIM ,  Kwang Jin MOON

IPC: H01L23/00 ,  H01L21/66

CPC classification number: H01L24/06 ,  H01L22/32 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/03845 ,  H01L2224/0392 ,  H01L2224/05022 ,  H01L2224/05084 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/0557 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/06515 ,  H01L2224/13111 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/80357 ,  H01L2224/80379 ,  H01L2224/80896 ,  H01L2924/05042 ,  H01L2924/0544 ,  H01L2924/059 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/1441 ,  H01L2924/1443 ,  H10B80/00

Abstract: A semiconductor package includes a substrate, a semiconductor layer on the substrate, a wiring structure on the semiconductor layer, a connection pad on and connected to the wiring structure, a test pad on and connected to the wiring structure, the test and connection pads being horizontally spaced from each other, a first liner film on the wiring structure and having a first bonding pad trench, a second liner film on the first liner film and having a second bonding pad trench, a first bonding pad including a barrier layer in contact with the first liner film and a metal layer on the barrier layer, and a second bonding pad filling an inner portion of the second bonding pad trench and in contact with the second liner film, wherein the second liner film integrally covers upper surfaces of the barrier layer and metal layer.

公开(公告)号：US20230282528A1

公开(公告)日：2023-09-07

申请号：US17897729

申请日：2022-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju Bin SEO ,  Su Jeong PARK ,  Seok Ho KIM ,  Kwang Jin MOON

IPC: H01L21/66 ,  H01L23/00

CPC classification number: H01L22/32 ,  H01L24/08 ,  H01L24/06 ,  H01L24/05 ,  H01L2224/08145 ,  H01L2224/06515 ,  H01L2224/05647 ,  H01L2224/05147 ,  H01L2224/80379 ,  H01L2924/05042 ,  H01L24/80

Abstract: A semiconductor package is provided. The semiconductor package includes a first semiconductor substrate, a first semiconductor element layer on an upper surface of the first semiconductor substrate, a first wiring structure on the first semiconductor element layer, a first connecting pad connected to the first wiring structure, a first test pad connected to the first wiring structure, a first front side bonding pad connected to the first connecting pad and including copper (Cu), and a second front side bonding pad connected to the first front side bonding pad and including copper (Cu) which has a nanotwin crystal structure different from a crystal structure of copper (Cu) included in the first front side bonding pad, wherein a width of the first front side bonding pad in the horizontal direction is different from a width of the second front side bonding pad in the horizontal direction.

公开(公告)号：US20230060360A1

公开(公告)日：2023-03-02

申请号：US17715103

申请日：2022-04-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju Bin SEO ,  Seok Ho KIM ,  Kwang Jin MOON

IPC: H01L23/00 ,  H01L25/065 ,  H01L21/66

Abstract: A semiconductor package that include first and second semiconductor chips bonded together, wherein the first semiconductor chip includes a first semiconductor substrate, a first semiconductor element layer and a first wiring structure sequentially stacked on a first surface of the first semiconductor substrate, first connecting pads and first test pads on the first wiring structure, and first front-side bonding pads, which are connected to the first connecting pads, wherein the second semiconductor chip includes a second semiconductor substrate, a second semiconductor element layer and a second wiring structure sequentially stacked on a third surface of the second semiconductor substrate, and first back-side bonding pads bonded to the first front-side bonding pads on the fourth surface of the second semiconductor substrate, and wherein the first test pads are not electrically connected to the second semiconductor chip.

公开(公告)号：US20190259744A1

公开(公告)日：2019-08-22

申请号：US16400465

申请日：2019-05-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho Jin LEE ,  Seok Ho KIM ,  Kwang Jin MOON ,  Byung Lyul PARK ,  Nae In LEE

IPC: H01L25/00 ,  H01L21/3065 ,  H01L21/768 ,  H01L21/308 ,  H01L23/00 ,  H01L25/065

Abstract: There is provided a method for fabricating a substrate structure capable of enhancing process reproducibility and process stability by trimming a bevel region of a substrate using a wafer level process. The method includes providing a first substrate including first and second surfaces opposite each other and a first device region formed at the first surface, providing a second substrate including third and fourth surfaces opposite each other and a second device region at the third surface, bonding the first substrate and the second substrate to electrically connect the first device region and the second device region, and forming a trimmed substrate. The forming the trimmed substrate includes etching an edge region of the second substrate bonded to the first substrate.

公开(公告)号：US20180226390A1

公开(公告)日：2018-08-09

申请号：US15869808

申请日：2018-01-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Pil Kyu KANG ,  Seok Ho KIM ,  Tae Yeong KIM ,  Kwang Jin MOON ,  Ho Jin LEE

IPC: H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L25/50 ,  H01L21/187 ,  H01L21/76898 ,  H01L24/80 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/08145 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/17181 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/73204 ,  H01L2224/80047 ,  H01L2224/80048 ,  H01L2224/8012 ,  H01L2224/80894 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80986 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06593 ,  H01L2924/3512 ,  H01L2224/80001 ,  H01L2224/81 ,  H01L2924/00014

Abstract: A method of manufacturing a substrate structure includes providing a first substrate including a first device region on a first surface, providing a second substrate including a second device region on a second surface, such that a width of the first device region is greater than a width of the second device region, and bonding the first substrate and the second substrate, such that the first and second device regions are facing each other and are electrically connected to each other.