公开(公告)号：US20180029809A1

公开(公告)日：2018-02-01

申请号：US15665954

申请日：2017-08-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Tak LEE ,  Sang Hak KIM ,  Bo Kyung KIM ,  Ji Ho SEO ,  Ho Jin LEE ,  Sang Hwa CHOI

IPC: B65G67/02 ,  A47L7/00 ,  A47L9/00 ,  F25D23/12 ,  A47L9/04 ,  F25D11/00 ,  F25D25/00 ,  A47L9/28 ,  A47L5/22

CPC classification number: B65G67/02 ,  A47L5/22 ,  A47L7/0085 ,  A47L7/009 ,  A47L9/009 ,  A47L9/0477 ,  A47L9/2852 ,  A47L9/2857 ,  A47L9/2873 ,  A47L9/2894 ,  A47L2201/02 ,  A47L2201/022 ,  A47L2201/04 ,  F25D11/00 ,  F25D23/12 ,  F25D25/005 ,  F25D2400/20

Abstract: Disclosed are a robot cleaner, a refrigerator, a container transfer system, and a method of transferring and retrieving a container using the robot cleaner. The method of transferring a container include returning a robot cleaner to a position guide device installed at a refrigerator, mounting the robot cleaner on the position guide device, transferring, by the refrigerator, a container built in the refrigerator to mount the container on the robot cleaner, and moving the robot cleaner on which the container is mounted to a target position.

公开(公告)号：US20230170386A1

公开(公告)日：2023-06-01

申请号：US17888639

申请日：2022-08-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ho Jin LEE ,  Beom Jin PARK ,  Myoung Sun LEE ,  Keun Hwi CHO ,  Dong Won KIM

IPC: H01L29/06 ,  H01L29/786 ,  H01L29/775 ,  H01L29/66

CPC classification number: H01L29/0673 ,  H01L29/775 ,  H01L29/6656 ,  H01L29/78696

Abstract: A semiconductor device includes first to fourth active patterns extending in a horizontal first direction. The second active pattern is spaced apart from the first active pattern in the first direction. The third active pattern is spaced apart from the first active pattern in a horizontal second direction. The fourth active pattern is spaced apart from the third active pattern in the first direction. A field insulating layer surrounds a sidewall of each of the first to fourth active patterns. First to fourth pluralities of nanosheets are respectively disposed the first to fourth active patterns. A first gate electrode extends in the second direction, intersects each of the first and third active patterns, and surrounds the first and third pluralities of nanosheets. A second gate electrode extends in the second direction, intersects each of the second and fourth active patterns, and surrounds the second and fourth pluralities of nanosheets.

公开(公告)号：US20190259744A1

公开(公告)日：2019-08-22

申请号：US16400465

申请日：2019-05-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho Jin LEE ,  Seok Ho KIM ,  Kwang Jin MOON ,  Byung Lyul PARK ,  Nae In LEE

IPC: H01L25/00 ,  H01L21/3065 ,  H01L21/768 ,  H01L21/308 ,  H01L23/00 ,  H01L25/065

Abstract: There is provided a method for fabricating a substrate structure capable of enhancing process reproducibility and process stability by trimming a bevel region of a substrate using a wafer level process. The method includes providing a first substrate including first and second surfaces opposite each other and a first device region formed at the first surface, providing a second substrate including third and fourth surfaces opposite each other and a second device region at the third surface, bonding the first substrate and the second substrate to electrically connect the first device region and the second device region, and forming a trimmed substrate. The forming the trimmed substrate includes etching an edge region of the second substrate bonded to the first substrate.

公开(公告)号：US20180226390A1

公开(公告)日：2018-08-09

申请号：US15869808

申请日：2018-01-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Pil Kyu KANG ,  Seok Ho KIM ,  Tae Yeong KIM ,  Kwang Jin MOON ,  Ho Jin LEE

IPC: H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L25/50 ,  H01L21/187 ,  H01L21/76898 ,  H01L24/80 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/08145 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/17181 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/73204 ,  H01L2224/80047 ,  H01L2224/80048 ,  H01L2224/8012 ,  H01L2224/80894 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80986 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06593 ,  H01L2924/3512 ,  H01L2224/80001 ,  H01L2224/81 ,  H01L2924/00014

Abstract: A method of manufacturing a substrate structure includes providing a first substrate including a first device region on a first surface, providing a second substrate including a second device region on a second surface, such that a width of the first device region is greater than a width of the second device region, and bonding the first substrate and the second substrate, such that the first and second device regions are facing each other and are electrically connected to each other.

公开(公告)号：US20180138164A1

公开(公告)日：2018-05-17

申请号：US15705427

申请日：2017-09-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho Jin LEE ,  Seok Ho Kim ,  Kwang Jin Moon ,  Byung Lyul Park ,  Nae In Lee

IPC: H01L25/00 ,  H01L23/00 ,  H01L21/3065 ,  H01L21/768 ,  H01L25/065

CPC classification number: H01L25/50 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3083 ,  H01L21/67 ,  H01L21/76898 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/89 ,  H01L24/92 ,  H01L25/0657 ,  H01L2224/08145 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/81895 ,  H01L2224/81896 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2924/00

Abstract: There is provided a method for fabricating a substrate structure capable of enhancing process reproducibility and process stability by trimming a bevel region of a substrate using a wafer level process. The method includes providing a first substrate including first and second surfaces opposite each other and a first device region formed at the first surface, providing a second substrate including third and fourth surfaces opposite each other and a second device region at the third surface, bonding the first substrate and the second substrate to electrically connect the first device region and the second device region, and forming a trimmed substrate. The forming the trimmed substrate includes etching an edge region of the second substrate bonded to the first substrate.