公开(公告)号：USD1037239S1

公开(公告)日：2024-07-30

申请号：US29888248

申请日：2023-03-29

Applicant: Samsung Electronics Co., Ltd.

Designer： Nam-Kyu Kim ,  Bum-Soo Park ,  Seung-Ho Jang

Abstract: FIG. 1 is a top front perspective view of a case for electronic device showing our new design;
FIG. 2 is a front view thereof;
FIG. 3 is a rear view thereof;
FIG. 4 is a left side view thereof;
FIG. 5 is a right side view thereof;
FIG. 6 is a top plan view thereof;
FIG. 7 is a bottom plan view thereof;
FIG. 8 is a bottom rear perspective view thereof;
FIG. 9 is an enlarged view of the delineated portion 9 in FIG. 1; and,
FIG. 10 is an enlarged view of the delineated portion 10 in FIG. 8.
The dashed broken lines in the figures depict portions of the case for electronic device that form no part of the claimed design.
The dot-dash broken lines in the figures delineating portions of the claimed design that are illustrated in enlargements form no part of the claimed design.

公开(公告)号：USD1037238S1

公开(公告)日：2024-07-30

申请号：US29888242

申请日：2023-03-29

Applicant: Samsung Electronics Co., Ltd.

Designer： Nam-Kyu Kim ,  Bum-Soo Park ,  Seung-Ho Jang

Abstract: FIG. 1 is a top front perspective view of a case for electronic device showing our new design;
FIG. 2 is a front view thereof;
FIG. 3 is a rear view thereof;
FIG. 4 is a left side view thereof;
FIG. 5 is a right side view thereof;
FIG. 6 is a top plan view thereof;
FIG. 7 is a bottom plan view thereof;
FIG. 8 is a bottom rear perspective view thereof;
FIG. 9 is an enlarged view of the delineated portion 9 in FIG. 1; and,
FIG. 10 is an enlarged view of the delineated portion 10 in FIG. 8.
The dashed broken lines in the figures depict portions of the case for electronic device that form no part of the claimed design.
The dot-dash broken lines in the figures delineating portions of the claimed design that are illustrated in enlargements form no part of the claimed design.

公开(公告)号：USD947826S1

公开(公告)日：2022-04-05

申请号：US29748342

申请日：2020-08-28

Applicant: Samsung Electronics Co., Ltd.

Designer： In-Shik Kim ,  Yun-Jin Kim ,  Nam-Kyu Kim ,  Hae-Sung Park

公开(公告)号：USD1040795S1

公开(公告)日：2024-09-03

申请号：US29888230

申请日：2023-03-29

Applicant: Samsung Electronics Co., Ltd.

Designer： Nam-Kyu Kim ,  Bum-Soo Park ,  Seung-Ho Jang

Abstract: FIG. 1 is a top front perspective view of a case for electronic device showing our new design;
FIG. 2 is a front view thereof;
FIG. 3 is a rear view thereof;
FIG. 4 is a left side view thereof;
FIG. 5 is a right side view thereof;
FIG. 6 is a top plan view thereof;
FIG. 7 is a bottom plan view thereof;
FIG. 8 is a bottom rear perspective view thereof;
FIG. 9 is an enlarged view of the delineated portion 9 in FIG. 1; and,
FIG. 10 is an enlarged view of the delineated portion 10 in FIG. 8.
The dashed broken lines in the figures depict portions of the case for electronic device that form no part of the claimed design.
The dot-dash broken lines in the figures delineating portions of the claimed design that are illustrated in enlargements form no part of the claimed design.

公开(公告)号：USD890864S1

公开(公告)日：2020-07-21

申请号：US29614770

申请日：2017-08-23

Applicant: Samsung Electronics Co., Ltd.

Designer： Su-Hyun Na ,  Woo-Jung Moon ,  Nam-Kyu Kim

公开(公告)号：USD946548S1

公开(公告)日：2022-03-22

申请号：US29748354

申请日：2020-08-28

Applicant: Samsung Electronics Co., Ltd.

Designer： In-Shik Kim ,  Yun-Jin Kim ,  Nam-Kyu Kim ,  Hae-Sung Park

公开(公告)号：USD946547S1

公开(公告)日：2022-03-22

申请号：US29748334

申请日：2020-08-28

Applicant: Samsung Electronics Co., Ltd.

Designer： In-Shik Kim ,  Yun-Jin Kim ,  Nam-Kyu Kim ,  Hae-Sung Park

公开(公告)号：US11004976B2

公开(公告)日：2021-05-11

申请号：US16351328

申请日：2019-03-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungkwan Kang ,  Keum Seok Park ,  Byeongchan Lee ,  Sangbom Kang ,  Nam-Kyu Kim

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/49 ,  H01L29/51 ,  H01L21/335

Abstract: A semiconductor device has a silicide source/drain region is fabricated by growing silicon on an epitaxial region including silicon and either germanium or carbon. In the method, a gate electrode is formed on a semiconductor substrate with a gate insulating layer interposed therebetween. An epitaxial layer is formed in the semiconductor substrate at both sides of the gate electrodes. A silicon layer is formed to cap the epitaxial layer. The silicon layer and a metal material are reacted to form a silicide layer. In a PMOS, the epitaxial layer has a top surface and inclined side surfaces that are exposed above the upper surface of the active region. The silicon layer is grown on the epitaxial layer in such a way as to cap the top and inclined surfaces.

公开(公告)号：US10263109B2

公开(公告)日：2019-04-16

申请号：US14995215

申请日：2016-01-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungkwan Kang ,  Keum Seok Park ,  Byeongchan Lee ,  Sangbom Kang ,  Nam-Kyu Kim

IPC: H01L21/8234 ,  H01L21/44 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/49 ,  H01L29/51

Abstract: A semiconductor device has a silicide source/drain region is fabricated by growing silicon on an epitaxial region including silicon and either germanium or carbon. In the method, a gate electrode is formed on a semiconductor substrate with a gate insulating layer interposed therebetween. An epitaxial layer is formed in the semiconductor substrate at both sides of the gate electrodes. A silicon layer is formed to cap the epitaxial layer. The silicon layer and a metal material are reacted to form a silicide layer. In a PMOS, the epitaxial layer has a top surface and inclined side surfaces that are exposed above the upper surface of the active region. The silicon layer is grown on the epitaxial layer in such a way as to cap the top and inclined surfaces.

公开(公告)号：US09530870B2

公开(公告)日：2016-12-27

申请号：US14805876

申请日：2015-07-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jieon Yoon ,  Seokhoon Kim ,  Gyeom Kim ,  Nam-Kyu Kim ,  JinBum Kim ,  Dong Chan Suh ,  Kwan Heum Lee ,  Byeongchan Lee ,  Choeun Lee ,  Sujin Jung

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L21/306 ,  H01L21/8234 ,  H01L21/324 ,  H01L29/04 ,  H01L21/265 ,  H01L29/165

CPC classification number: H01L29/66795 ,  H01L21/26506 ,  H01L21/30608 ,  H01L21/3247 ,  H01L21/823425 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7848

Abstract: Provided is a method of fabricating a semiconductor device. The method includes forming a gate pattern on a semiconductor substrate, injecting amorphization elements into the semiconductor substrate to form an amorphous portion at a side of the gate pattern, removing the amorphous portion to form a recess region, and forming a source/drain pattern in the recess region. When the recess region is formed, an etch rate of the amorphous portion is substantially the same in two different directions (e.g., and any other direction) of the semiconductor substrate.

Abstract translation: 提供一种制造半导体器件的方法。 该方法包括在半导体衬底上形成栅极图案，将非晶化元件注入到半导体衬底中以在栅极图案的一侧形成非晶部分，去除非晶部分以形成凹陷区域，并且形成源极/漏极图案 凹陷区域。 当形成凹陷区域时，非晶部分的蚀刻速率在半导体衬底的两个不同方向（例如，<111>和任何其它方向）上基本相同。