公开(公告)号：US10756211B2

公开(公告)日：2020-08-25

申请号：US15379190

申请日：2016-12-14

申请人： Samsung Electronics Co., Ltd.

发明人： Keum Seok Park ,  Jungho Yoo ,  Jinyeong Joe ,  Bonyoung Koo ,  Dongsuk Shin ,  Hongsik Yoon ,  Byeongchan Lee

IPC分类号： H01L29/78 ,  H01L29/165 ,  H01L29/66 ,  H01L21/02 ,  H01L29/06 ,  H01L29/08 ,  H01L29/45

摘要： A semiconductor device includes an active pattern protruding from a substrate, a gate structure crossing over the active pattern, and source/drain regions disposed on the active pattern at opposite sides of the gate structure. Each of the source/drain regions includes a first epitaxial pattern contacting the active pattern and a second epitaxial pattern on the first epitaxial pattern. The first epitaxial pattern comprises a material having a lattice constant which is the same as that of the substrate, and the second epitaxial pattern comprises a material having a lattice constant greater than that of the first epitaxial pattern.

公开(公告)号：US09691902B2

公开(公告)日：2017-06-27

申请号：US14990398

申请日：2016-01-07

申请人： Samsung Electronics Co., Ltd.

发明人： Myungil Kang ,  Yoonhae Kim ,  Byeongchan Lee

IPC分类号： H01L29/78 ,  H01L29/417 ,  H01L27/092 ,  H01L29/423

CPC分类号： H01L29/7848 ,  H01L21/823418 ,  H01L21/823431 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/41725 ,  H01L29/4232 ,  H01L29/785

摘要： A semiconductor device includes a first pattern on a first active region, a second pattern on a second active region, and a third pattern on a third active region. The first pattern is spaced from the second pattern by a first interval corresponding to the width of a first recess between the first and second active regions. The second pattern is spaced from the third pattern by a second interval corresponding to the width of a second recess between the second and third active regions. The first, second, and third patterns includes gate patterns, and the first and second recesses include semiconductor material with a conductivity type different from the active regions. The semiconductor material in one recess extends higher than the semiconductor material in the other recess. The first, second, and third patterns have the same width, and the first and second recesses have different depths.

公开(公告)号：US09553190B2

公开(公告)日：2017-01-24

申请号：US14673519

申请日：2015-03-30

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Keum Seok Park ,  Jungho Yoo ,  Jinyeong Joe ,  Bonyoung Koo ,  Dongsuk Shin ,  Hongsik Yoon ,  Byeongchan Lee

IPC分类号： H01L29/772 ,  H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L29/165

CPC分类号： H01L29/7848 ,  H01L21/02532 ,  H01L21/02636 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/785

摘要： A semiconductor device includes an active pattern protruding from a substrate, a gate structure crossing over the active pattern, and source/drain regions disposed on the active pattern at opposite sides of the gate structure. Each of the source/drain regions includes a first epitaxial pattern contacting the active pattern and a second epitaxial pattern on the first epitaxial pattern. The first epitaxial pattern comprises a material having a lattice constant which is the same as that of the substrate, and the second epitaxial pattern comprises a material having a lattice constant greater than that of the first epitaxial pattern.

摘要翻译： 半导体器件包括从衬底突出的有源图案，在有源图案上交叉的栅极结构以及设置在栅极结构的相对侧上的有源图案上的源极/漏极区域。 源极/漏极区域中的每一个包括接触有源图案的第一外延图案和第一外延图案上的第二外延图案。 第一外延图案包括具有与衬底相同的晶格常数的材料，并且第二外延图案包括具有大于第一外延图案的晶格常数的晶格常数的材料。

公开(公告)号：US20190214498A1

公开(公告)日：2019-07-11

申请号：US16351328

申请日：2019-03-12

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Sungkwan Kang ,  Keum Seok Park ,  Byeongchan Lee ,  Sangbom Kang ,  Nam-Kyu Kim

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/49 ,  H01L29/51 ,  H01L29/08 ,  H01L21/8238

CPC分类号： H01L29/7848 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/0847 ,  H01L29/4975 ,  H01L29/51 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636

摘要： A semiconductor device has a silicide source/drain region is fabricated by growing silicon on an epitaxial region including silicon and either germanium or carbon. In the method, a gate electrode is formed on a semiconductor substrate with a gate insulating layer interposed therebetween. An epitaxial layer is formed in the semiconductor substrate at both sides of the gate electrodes. A silicon layer is formed to cap the epitaxial layer. The silicon layer and a metal material are reacted to form a silicide layer. In a PMOS, the epitaxial layer has a top surface and inclined side surfaces that are exposed above the upper surface of the active region. The silicon layer is grown on the epitaxial layer in such a way as to cap the top and inclined surfaces.

公开(公告)号：US10079305B2

公开(公告)日：2018-09-18

申请号：US14861748

申请日：2015-09-22

申请人： Samsung Electronics Co., Ltd.

发明人： Byeongchan Lee ,  Nam-Kyu Kim ,  JinBum Kim ,  Kwan Heum Lee ,  Choeun Lee ,  Sujin Jung

IPC分类号： H01L29/06 ,  H01L29/165 ,  H01L29/78 ,  H01L21/02 ,  H01L21/76 ,  H01L29/08 ,  H01L29/66

CPC分类号： H01L29/7851 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848

摘要： Provided are a semiconductor device and a method of fabricating the same. The device may include an active pattern protruding from a substrate, gate structures crossing the active pattern, and a source/drain region provided between adjacent ones of the gate structures. The source/drain region may include a source/drain epitaxial layer in a recessed region, which is formed in the active pattern between the adjacent ones of the gate structures. Further, an impurity diffusion region may be provided in the active pattern to enclose the source/drain epitaxial layer along inner surfaces of the recessed region.

公开(公告)号：US09853160B2

公开(公告)日：2017-12-26

申请号：US15135566

申请日：2016-04-22

申请人： Samsung Electronics Co., Ltd.

发明人： Sujin Jung ,  JinBum Kim ,  Kang Hun Moon ,  Kwan Heum Lee ,  Byeongchan Lee ,  Choeun Lee ,  Yang Xu

IPC分类号： H01L27/088 ,  H01L29/78 ,  H01L29/08 ,  H01L29/66

CPC分类号： H01L29/7851 ,  H01L29/0847 ,  H01L29/66795 ,  H01L29/7848

摘要： A semiconductor device is disclosed. The device includes a substrate including an active region defined by a device isolation layer, a fin pattern protruding from the substrate and extending in a first direction, the fin pattern including a gate fin region and a source/drain fin region, a gate pattern disposed on the gate fin region to extend in a second direction crossing the first direction, and a source/drain portion provided on a sidewall of the source/drain fin region. When measured in the second direction, a width of the source/drain fin region is different from a width in the second direction of the gate fin region.

公开(公告)号：US20150031183A1

公开(公告)日：2015-01-29

申请号：US14485035

申请日：2014-09-12

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Sungkwan Kang ,  Keum Seok Park ,  Byeongchan Lee ,  Sangbom Kang ,  Nam-Kyu Kim

IPC分类号： H01L29/66

CPC分类号： H01L29/7848 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/0847 ,  H01L29/4975 ,  H01L29/51 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636

摘要： A semiconductor device has a silicide source/drain region is fabricated by growing silicon on an epitaxial region including silicon and either germanium or carbon. In the method, a gate electrode is formed on a semiconductor substrate with a gate insulating layer interposed therebetween. An epitaxial layer is formed in the semiconductor substrate at both sides of the gate electrodes. A silicon layer is formed to cap the epitaxial layer. The silicon layer and a metal material are reacted to form a silicide layer. In a PMOS, the epitaxial layer has a top surface and inclined side surfaces that are exposed above the upper surface of the active region. The silicon layer is grown on the epitaxial layer in such a way as to cap the top and inclined surfaces.

摘要翻译： 通过在包括硅和锗或锗的外延区域上生长硅来制造具有硅化物源极/漏极区的半导体器件。 在该方法中，在半导体衬底上形成有栅极绝缘层的栅电极。 在栅极两侧的半导体衬底中形成外延层。 形成硅层来覆盖外延层。 硅层和金属材料反应形成硅化物层。 在PMOS中，外延层具有暴露在有源区的上表面上方的顶表面和倾斜侧表面。 硅层在外延层上生长，以覆盖顶部和倾斜表面。

公开(公告)号：US10319859B2

公开(公告)日：2019-06-11

申请号：US15844863

申请日：2017-12-18

申请人： Samsung Electronics Co., Ltd.

发明人： Sujin Jung ,  JinBum Kim ,  Kang Hun Moon ,  Kwan Heum Lee ,  Byeongchan Lee ,  Choeun Lee ,  Yang Xu

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L21/8234

摘要： A semiconductor device is disclosed. The device includes a substrate including an active region defined by a device isolation layer, a fin pattern protruding from the substrate and extending in a first direction, the fin pattern including a gate fin region and a source/drain fin region, a gate pattern disposed on the gate fin region to extend in a second direction crossing the first direction, and a source/drain portion provided on a sidewall of the source/drain fin region. When measured in the second direction, a width of the source/drain fin region is different from a width in the second direction of the gate fin region.

公开(公告)号：US10170622B2

公开(公告)日：2019-01-01

申请号：US15619882

申请日：2017-06-12

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Sungkwan Kang ,  Keum Seok Park ,  Byeongchan Lee ,  Sangbom Kang ,  Nam-Kyu Kim

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/49 ,  H01L29/51 ,  H01L21/335

摘要： A semiconductor device has a silicide source/drain region is fabricated by growing silicon on an epitaxial region including silicon and either germanium or carbon. In the method, a gate electrode is formed on a semiconductor substrate with a gate insulating layer interposed therebetween. An epitaxial layer is formed in the semiconductor substrate at both sides of the gate electrodes. A silicon layer is formed to cap the epitaxial layer. The silicon layer and a metal material are reacted to form a silicide layer. In a PMOS, the epitaxial layer has a top surface and inclined side surfaces that are exposed above the upper surface of the active region. The silicon layer is grown on the epitaxial layer in such a way as to cap the top and inclined surfaces.

公开(公告)号：US20170278967A1

公开(公告)日：2017-09-28

申请号：US15619882

申请日：2017-06-12

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Sungkwan Kang ,  Keum Seok Park ,  Byeongchan Lee ,  Sangbom Kang ,  Nam-Kyu Kim

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/08 ,  H01L29/51 ,  H01L21/02

CPC分类号： H01L29/7848 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/0847 ,  H01L29/4975 ,  H01L29/51 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636

摘要： A semiconductor device has a silicide source/drain region is fabricated by growing silicon on an epitaxial region including silicon and either germanium or carbon. In the method, a gate electrode is formed on a semiconductor substrate with a gate insulating layer interposed therebetween. An epitaxial layer is formed in the semiconductor substrate at both sides of the gate electrodes. A silicon layer is formed to cap the epitaxial layer. The silicon layer and a metal material are reacted to form a silicide layer. In a PMOS, the epitaxial layer has a top surface and inclined side surfaces that are exposed above the upper surface of the active region. The silicon layer is grown on the epitaxial layer in such a way as to cap the top and inclined surfaces.