公开(公告)号：US20160202320A1

公开(公告)日：2016-07-14

申请号：US14714283

申请日：2015-05-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Rohit NATARAJAN

IPC: G01R31/317 ,  G01R31/3177

CPC classification number: G01R31/31704 ,  G01R31/31705 ,  G06F11/3466 ,  G06F11/3476 ,  G06F11/348

Abstract: A system and corresponding method captures speculative and concurrent trace-data and trace-clock information from core processing units of a System on a Chip (SOC). An interface receives trace data from at least one core processing unit, and a storage array stores the trace data in two different modes of operation. In the first mode, which occurs prior to a predetermined operating state of the SOC, the storage array operates in a circular buffer mode in which the newest trace data overwrites the oldest trace data when the storage array becomes full In the second mode, which occurs after the predetermined operating state of the SOC, the storage array operates in a FIFO mode in which the newest trace data is written into the storage array and the oldest trace data contained in the storage array is output to a debug processing core unit of the SOC.

Abstract translation: 系统和相应的方法从芯片系统（SOC）的核心处理单元捕获推测性和并发跟踪数据和跟踪时钟信息。 接口从至少一个核心处理单元接收跟踪数据，并且存储阵列将跟踪数据存储在两种不同的操作模式中。 在SOC的预定操作状态之前发生的第一模式中，存储阵列以循环缓冲模式操作，其中最新的跟踪数据在存储阵列变满时覆盖最早的跟踪数据在发生的第二模式中 在SOC的预定操作状态之后，存储阵列以FIFO模式操作，其中最新的跟踪数据被写入存储阵列，并且包含在存储阵列中的最早的跟踪数据被输出到SOC的调试处理核心单元 。

公开(公告)号：US20160363986A1

公开(公告)日：2016-12-15

申请号：US14735119

申请日：2015-06-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ian SWARBRICK ,  Michael BEKERMAN ,  Rohit NATARAJAN

IPC: G06F1/32 ,  G06F1/26 ,  G06F13/42

CPC classification number: G06F13/4282 ,  G06F1/3206 ,  G06F1/3253 ,  G06F1/3287 ,  Y02D10/151 ,  Y02D10/171

Abstract: A system and a method select a datapath through a meshed Input/Output (IO) fabric. A plurality of port controllers is coupled to interconnection logic. Each port controller is coupled to a corresponding communication link and outputs a detection signal if the corresponding communication link transitions from a first lower-power state to a second higher power state. The interconnection logic, responsive to the detection signal, is configured to output a first signal to one or more selected port controllers to transition the corresponding communication link coupled to the selected port controller from the first power state to the second power state based on a frequency of use of a datapath between the communication link corresponding to the port controller outputting the detection signal and the communication link corresponding to each of the one or more selected port controllers.

Abstract translation: 系统和方法通过网格输入/输出（IO）结构选择数据路径。 多个端口控制器耦合到互连逻辑。 如果对应的通信链路从第一低功率状态转换到第二较高功率状态，则每个端口控制器耦合到对应的通信链路并输出检测信号。 互连逻辑响应于检测信号被配置为将第一信号输出到一个或多个选择的端口控制器，以将耦合到所选端口控制器的对应通信链路从第一功率状态转换到第二功率状态，基于频率 在与输出检测信号的端口控制器相对应的通信链路与对应于一个或多个所选端口控制器中的每一个的通信链路之间使用数据路径。