公开(公告)号：US20180261540A1

公开(公告)日：2018-09-13

申请号：US15679444

申请日：2017-08-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joon-gon LEE ,  Ryuji TOMITA ,  Do-sun LEE ,  Chul-sung KIM ,  Do-hyun LEE

IPC: H01L23/522 ,  H01L29/78 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L21/76843 ,  H01L23/53204 ,  H01L29/785

Abstract: An integrated circuit device includes at least one fin-type active region, a gate line on the at least one fin-type active region, and a source/drain region on the at least one fin-type active region at at least one side of the gate line. A first conductive plug is connected to the source/drain region and includes cobalt. A second conductive plug is connected to the gate line and spaced apart from the first conductive plug. A third conductive plug is connected to each of the first conductive plug and the second conductive plug. The third conductive plug electrically connects the first conductive plug and the second conductive plug.

公开(公告)号：US20180090495A1

公开(公告)日：2018-03-29

申请号：US15473031

申请日：2017-03-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Do Sun LEE ,  Joon Gon LEE ,  Na Rae KIM ,  Chul Sung KIM ,  Do Hyun LEE ,  Ryuji TOMITA ,  Sang Jin HYUN

IPC: H01L27/092 ,  H01L29/165 ,  H01L29/45 ,  H01L29/417 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L21/02 ,  H01L21/285

CPC classification number: H01L27/0924 ,  H01L21/02532 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/4175 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/7856

Abstract: Semiconductor devices may have a first semiconductor element including first active regions that are doped with a first conductivity-type impurity and that are on a semiconductor substrate, a first gate structure between the first active regions, and first contacts connected to the first active regions, respectively; and a second semiconductor element including second active regions that are doped with a second conductivity-type impurity different from the first conductivity-type impurity and that are on the semiconductor substrate, a second gate structure between the second active regions, and second contacts connected to the second active regions, respectively, and having a second length greater than a first length of each of the first contacts in a first direction parallel to an upper surface of the semiconductor substrate.