公开(公告)号：US20240258391A1

公开(公告)日：2024-08-01

申请号：US18323323

申请日：2023-05-24

申请人： SK hynix Inc.

发明人： Rho Gyu KWAK ,  In Su PARK ,  Jung Shik JANG ,  Jung Dal CHOI ,  Seok Min CHOI ,  Won Geun CHOI

IPC分类号： H01L29/423 ,  H01L23/528 ,  H01L23/532

CPC分类号： H01L29/42356 ,  H01L23/5283 ,  H01L23/53204 ,  H01L23/5329

摘要： A semiconductor device according to an embodiment of the present disclosure includes a first cell area and a second cell area adjacent to each other in a first direction, a support disposed between the first cell area and the second cell area, first gate lines stacked in the first cell area, first pads configured to extend from the first gate lines and configured to protrude upward along a first sidewall of the support, second gate lines stacked in the second cell area, second pads configured to extend from the second gate lines and configured to protrude upward along a second sidewall of the support, and first connection pads configured to extend in the first direction along a third sidewall of the support and configured to electrically connect the first pads with the second pads.

公开(公告)号：US20240145381A1

公开(公告)日：2024-05-02

申请号：US18407517

申请日：2024-01-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shin-Yi Yang ,  Hsin-Yen Huang ,  Ming-Han Lee ,  Shau-Lin Shue ,  Yu-Chen Chan ,  Meng-Pei Lu

IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L23/532

CPC分类号： H01L23/5226 ,  H01L21/76802 ,  H01L21/76841 ,  H01L21/76877 ,  H01L23/53204

摘要： In some embodiments, the present disclosure relates an integrated chip including a substrate. A conductive interconnect feature is arranged over the substrate. The conductive interconnect feature has a base feature portion with a base feature width and an upper feature portion with an upper feature width. The upper feature width is narrower than the base feature width such that the conductive interconnect feature has tapered outer feature sidewalls. An interconnect via is arranged over the conductive interconnect feature. The interconnect via has a base via portion with a base via width and an upper via portion with an upper via width. The upper via width is wider than the base via width such that the interconnect via has tapered outer via sidewalls.

公开(公告)号：US11728336B2

公开(公告)日：2023-08-15

申请号：US16941729

申请日：2020-07-29

申请人： NXP USA, Inc.

发明人： Robert S. Jones, III ,  Xiankun Jin

IPC分类号： H01L27/08 ,  H01L23/532 ,  H01L23/522 ,  H03M1/00 ,  H01L49/02

CPC分类号： H01L27/0805 ,  H01L23/5223 ,  H01L23/53204 ,  H01L28/60 ,  H01L28/87 ,  H03M1/00

摘要： Embodiments are provided for a capacitive array including: a first row of alternating first fingers and second fingers formed in a first conductive layer, wherein each first and second finger has a uniform width in a first direction and a uniform length in a second direction perpendicular to the first direction, the first row of alternating first and second fingers include a same integer number of first fingers and second fingers, and the first and second fingers are interdigitated in the first direction; and a first compensation finger formed in the first conductive layer at an end of the first row of alternating first and second fingers nearest a first outer boundary of the capacitive array, the first compensation finger configured to have an opposite polarity as a neighboring finger on the end of the first row.

公开(公告)号：US20230189516A1

公开(公告)日：2023-06-15

申请号：US17648783

申请日：2022-01-24

申请人： Yangtze Memory Technologies Co., Ltd.

发明人： Tao Yang ,  DongXue Zhao ,  Yuancheng Yang ,  Lei Liu ,  Kun Zhang ,  Di Wang ,  Wenxi Zhou ,  ZhiLiang Xia ,  ZongLiang Huo

IPC分类号： H01L27/11556 ,  G11C5/02 ,  H01L27/11582 ,  H01L23/532

CPC分类号： H01L27/11556 ,  G11C5/025 ,  H01L27/11582 ,  H01L23/53204

摘要： The present disclosure is directed to a memory structure including a staircase structure. The staircase structure can include a bottom select gate, a plate line formed above the bottom select gate, and a word line formed above the plate line. The pillar can extend through the bottom select gate, the plate line, and the word line. The memory structure can also include a source structure formed under the pillar and a drain cap formed above the pillar. The memory structure can further include a bit line formed above the drain cap.

公开(公告)号：US11670593B2

公开(公告)日：2023-06-06

申请号：US17120298

申请日：2020-12-14

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tsung-Fu Tsai ,  Hou-Ju Huang ,  Shih-Ting Lin ,  Szu-Wei Lu ,  Hung-Wei Tsai

IPC分类号： H01L23/532 ,  H01L23/29 ,  H01L21/48 ,  H01L21/56 ,  H01L23/538

CPC分类号： H01L23/53204 ,  H01L21/4857 ,  H01L21/56 ,  H01L23/29 ,  H01L23/5383

摘要： An electronic device and a manufacturing method thereof are provided. The method includes at least the following steps. An insulating encapsulant is formed to encapsulate a multi-layered structure and a semiconductor die, where the multi-layered structure includes a first conductor, a diffusion barrier layer on the first conductor, and a metallic layer on the diffusion barrier layer, and the insulating encapsulant at least exposes a portion of the semiconductor die and a portion of the first conductor. A redistribution structure is formed over the insulating encapsulant, the semiconductor die, and the first conductor. The metallic layer is removed to form a recess in the insulating encapsulant. A second conductor is formed in the recess over the diffusion barrier layer, where the first conductor, the diffusion barrier layer, and the second conductor form a conductive structure that is electrically coupled to the semiconductor die through the redistribution structure.

公开(公告)号：US20180294273A1

公开(公告)日：2018-10-11

申请号：US15481676

申请日：2017-04-07

申请人： MACRONIX INTERNATIONAL CO., LTD.

发明人： Ting-Feng Liao ,  Yi-Chen Wang

IPC分类号： H01L27/11556 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  G11C16/04

CPC分类号： H01L27/11556 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53204 ,  H01L23/53295

摘要： A memory device includes a semiconductor substrate, a first conductive layer, a plurality of second conductive layers, a plurality insulating layers, at least one contact plug and at least one dummy plug. The first conductive layer is disposed on the semiconductor substrate. The insulating layers are disposed on the first conductive layer. The second conductive layers are alternatively stacked with the insulating layers and insulated from the first conductive layer. The contact plug passes through the insulating layers and the second conductive layers, insulates from the second conductive layers and electrically contacts to the first conductive layer. The dummy plug, corresponds to the at least one contact plug, passes through the insulating layers and the second conductive layers, and insulates from the second conductive layers and the first conductive layer.

公开(公告)号：US20180218993A1

公开(公告)日：2018-08-02

申请号：US15936748

申请日：2018-03-27

申请人： Texas Instruments Incorporated

发明人： HELMUT RINCK ,  GERNOT BAUER ,  ROBERT ZRILE ,  KAI-ALEXANDER SCHACHTSCHNEIDER ,  MICHAEL OTTE ,  HARALD WIESNER

IPC分类号： H01L23/00 ,  H01L23/532 ,  H01L23/522

CPC分类号： H01L24/13 ,  H01L23/5226 ,  H01L23/53204 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/94 ,  H01L2224/0345 ,  H01L2224/03612 ,  H01L2224/03614 ,  H01L2224/03622 ,  H01L2224/03828 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05157 ,  H01L2224/05558 ,  H01L2224/05657 ,  H01L2224/11005 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/94 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/2064 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2924/01078 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/01051

摘要： A method of forming bond pads includes providing a substrate including an integrated circuit (IC) device formed thereon having an oxidizable uppermost metal interconnect layer which provides a plurality of bond pads that are coupled to circuit nodes on the IC device. The plurality of bond pads includes a metal bond pad area. A cobalt including connection layer is deposited directly on the metal bond pad area. The cobalt including connection layer is patterned to provide a cobalt bond pad surface for the plurality of bond pads, and a solder material is formed on the cobalt bond pad surface.

公开(公告)号：US09960149B2

公开(公告)日：2018-05-01

申请号：US14994967

申请日：2016-01-13

申请人： Freescale Semiconductor, Inc.

发明人： Michael B. Vincent ,  Scott M. Hayes

IPC分类号： H01L23/31 ,  H01L23/532 ,  H01L25/065 ,  H01L25/00 ,  H01L21/56 ,  H01L23/00 ,  H01L25/10 ,  H01L23/528

CPC分类号： H01L25/0657 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/528 ,  H01L23/53204 ,  H01L23/5328 ,  H01L23/5329 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2225/06524 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/1035 ,  H01L2225/1064 ,  H01L2225/1076 ,  H01L2924/12042 ,  H01L2924/1815 ,  H01L2924/00

摘要： Embodiments of methods for forming a device include performing an oxidation inhibiting treatment to exposed ends of first and second device-to-edge conductors, and forming a package surface conductor to electrically couple the exposed ends of the first and second device-to-edge conductors. Performing the oxidation inhibiting treatment may include applying an organic solderability protectant coating to the exposed ends, or plating the exposed ends with a conductive plating material. The method may further include applying a conformal protective coating over the package surface conductor. An embodiment of a device formed using such a method includes a package body, the first and second device-to-edge conductors, the package surface conductor on a surface of the package body and extending between the first and second device-to-edge conductors, and the conformal protective coating over the package surface conductor.

公开(公告)号：US09824984B2

公开(公告)日：2017-11-21

申请号：US14438341

申请日：2013-10-25

申请人： IHP GmbH—Innovations for High Performance Microelectronics/Leibniz-Institut Fur Innovative Mikroelektronik

发明人： Zoya Dyka ,  Peter Langendorfer

IPC分类号： H01L23/48 ,  H01L23/00 ,  H01L23/532 ,  H01L23/528 ,  H01L27/118 ,  H01L27/02 ,  H01L23/522

CPC分类号： H01L23/573 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5286 ,  H01L23/53204 ,  H01L27/0292 ,  H01L27/11807 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device, in particular an integrated circuit with protection against side channel attacks, in particular imaging- and probing-based attacks, EMA and reverse engineering, in which a metallic conductive layer of a first (104) and/or a second potential supply line (106) are each connected directly and individually to all the circuit components via respective individual conductor path structures (V1, V2).

公开(公告)号：US09728485B1

公开(公告)日：2017-08-08

申请号：US15016886

申请日：2016-02-05

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ming-Han Lee ,  Shau-Lin Shue

IPC分类号： H01L23/373 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768

CPC分类号： H01L23/3736 ,  H01L21/76804 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76847 ,  H01L21/76879 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53204

摘要： A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a dielectric layer over the semiconductor substrate. The semiconductor device structure also includes a conductive feature in the dielectric layer, and the conductive feature includes a catalyst layer and a conductive element. The catalyst layer is between the conductive element and the dielectric layer, and the catalyst layer is in physical contact with the conductive element. The catalyst layer continuously surrounds a sidewall and a bottom of the conductive element. The catalyst layer is made of a material different from that of the conductive element, and the catalyst layer is capable of lowering a formation temperature of the conductive element.