公开(公告)号：US20180068889A1

公开(公告)日：2018-03-08

申请号：US15624783

申请日：2017-06-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junghun CHOI ,  Jeong Ik KIM ,  Myung YANG ,  Chul Sung KIM ,  Sang Jin HYUN

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/535

CPC classification number: H01L21/76862 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76876 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/535

Abstract: A semiconductor device and a method of manufacturing the same, the semiconductor device including a substrate; an insulating layer on the substrate, the insulating layer including a first trench and a second trench therein, the second trench having an aspect ratio that is smaller than an aspect ratio of the first trench; a barrier layer in the first trench and the second trench; a seed layer on the barrier layer in the first trench and the second trench; a first bulk layer on the seed layer and filled in the first trench; and a second bulk layer on the seed layer and filled in the second trench, wherein an average grain size of the second bulk layer is larger than an average grain size of the first bulk layer.

公开(公告)号：US20180151556A1

公开(公告)日：2018-05-31

申请号：US15683050

申请日：2017-08-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyo Seok CHOI ,  Chul Sung KIM ,  Jae Eun LEE

IPC: H01L27/06 ,  H01L29/78 ,  H01L49/02 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L27/0629 ,  H01L23/485 ,  H01L28/20 ,  H01L28/24 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/775 ,  H01L29/7831 ,  H01L29/785

Abstract: A semiconductor device includes a substrate, a first recess formed in the substrate, a first source/drain filling the first recess, a vertical metal resistor on the first source/drain, and an insulating liner separating the metal resistor from the first source/drain, with the vertical metal resistor being between two gate electrodes.

公开(公告)号：US20250063788A1

公开(公告)日：2025-02-20

申请号：US18431190

申请日：2024-02-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Min CHO ,  Hee Sub KIM ,  Bo Mi KIM ,  Chul Sung KIM ,  Geun Hee JEONG

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: The semiconductor device includes a substrate, first and second active patterns extending in a first direction, the second active pattern spaced apart from the first active pattern in a second direction different from the first direction, a gate electrode extending in the second direction, a first and second source/drain region each on one side of the gate electrode, a first and second source/drain contact each extending in the second direction on and connected to the first and second source/drain region respectively, and a contact separation layer separating the first and second source/drain contacts, the contact separation layer including a first portion and a second portion on first portion both between the first and second source/drain regions, wherein a width of the first portion of the contact separation layer in the first direction is greater than a width of the second portion of the contact separation layer in the first direction.

公开(公告)号：US20180090495A1

公开(公告)日：2018-03-29

申请号：US15473031

申请日：2017-03-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Do Sun LEE ,  Joon Gon LEE ,  Na Rae KIM ,  Chul Sung KIM ,  Do Hyun LEE ,  Ryuji TOMITA ,  Sang Jin HYUN

IPC: H01L27/092 ,  H01L29/165 ,  H01L29/45 ,  H01L29/417 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L21/02 ,  H01L21/285

CPC classification number: H01L27/0924 ,  H01L21/02532 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/4175 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/7856

Abstract: Semiconductor devices may have a first semiconductor element including first active regions that are doped with a first conductivity-type impurity and that are on a semiconductor substrate, a first gate structure between the first active regions, and first contacts connected to the first active regions, respectively; and a second semiconductor element including second active regions that are doped with a second conductivity-type impurity different from the first conductivity-type impurity and that are on the semiconductor substrate, a second gate structure between the second active regions, and second contacts connected to the second active regions, respectively, and having a second length greater than a first length of each of the first contacts in a first direction parallel to an upper surface of the semiconductor substrate.