公开(公告)号：US20210384068A1

公开(公告)日：2021-12-09

申请号：US17410149

申请日：2021-08-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNG DAE SUK ,  SANG HOON LEE ,  MASUOKA SADAAKI ,  HAN SU OH

IPC: H01L21/762 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786

Abstract: A semiconductor device includes: a pair of wire patterns configured to extend in a first direction and formed on a substrate to be spaced apart from each other in a second direction, the pair of wire patterns disposed closest to each other in the second direction; a gate electrode configured to extend in the second direction on the substrate, the gate electrode configured to surround the wire patterns; and first isolation layers configured to extend in the first direction between the substrate and the gate electrode and formed to be spaced apart from each other in the second direction, the first isolation layers overlapping the pair of wire patterns in a third direction perpendicular to the first and second directions.

公开(公告)号：US20200328107A1

公开(公告)日：2020-10-15

申请号：US16915050

申请日：2020-06-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNG DAE SUK ,  SANG HOON LEE ,  MASUOKA SADAAKI ,  HAN SU OH

IPC: H01L21/762 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786

Abstract: A semiconductor device includes: a pair of wire patterns configured to extend in a first direction and formed on a substrate to be spaced apart from each other in a second direction, the pair of wire patterns disposed closest to each other in the second direction; a gate electrode configured to extend in the second direction on the substrate, the gate electrode configured to surround the wire patterns; and first isolation layers configured to extend in the first direction between the substrate and the gate electrode and formed to be spaced apart from each other in the second direction, the first isolation layers overlapping the pair of wire patterns in a third direction perpendicular to the first and second directions.

公开(公告)号：US20210249413A1

公开(公告)日：2021-08-12

申请号：US17243943

申请日：2021-04-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： CHANG WOO NOH ,  MYUNG GIL KANG ,  GEUM JONG BAE ,  DONG IL BAE ,  JUNG GIL YANG ,  SANG HOON LEE

IPC: H01L27/092 ,  H01L29/66 ,  H01L21/033 ,  H01L29/78 ,  H01L29/08 ,  H01L21/8238 ,  H01L29/10

Abstract: Semiconductor devices are provided. The semiconductor devices may include a first wire pattern extending in a first direction on a substrate and a second wire pattern on the first wire pattern. The second wire pattern may be spaced apart from the first wire pattern and extends in the first direction. The semiconductor devices may also include a first gate structure at least partially surrounding the first wire pattern and the second wire pattern, a second gate structure spaced apart from the first gate structure in the first direction, a first source/drain region between the first gate structure and the second gate structure, a first spacer between a bottom surface of the first source/drain region and the substrate, a first source/drain contact on the first source/drain region, and a second spacer between the first source/drain contact and the first gate structure.

公开(公告)号：US20160062688A1

公开(公告)日：2016-03-03

申请号：US14744104

申请日：2015-06-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： OH CHUL KWON ,  SANG HOON LEE

IPC: G06F3/06

CPC classification number: G06F12/0246 ,  G06F2212/7203

Abstract: A flash memory device includes: a memory unit that includes a cell area that has one or more memory blocks each including a plurality of pages; a page buffer that includes a valid data area storing valid data to be programmed to the pages and a pad area storing non-valid data to be programmed to the pages, in response to an external data program command for the one or more pages; and a control logic that retains the non-valid data stored in the pad area and stores the valid data in the valid data area, in response to the data program command.

Abstract translation: 闪存装置包括：存储单元，其包括具有一个或多个存储块的单元区域，每个存储块包括多个页面; 页面缓冲器，其响应于所述一个或多个页面的外部数据程序命令，包括存储要编程到页面的有效数据的有效数据区域和存储要被编程到页面的无效数据的焊盘区域; 以及控制逻辑，其保存存储在所述焊盘区域中的所述非有效数据，并且响应于所述数据程序命令将所述有效数据存储在所述有效数据区域中。