公开(公告)号：US20220020859A1

公开(公告)日：2022-01-20

申请号：US17192959

申请日：2021-03-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： KEUN HWI CHO ,  SOONMOON JUNG ,  DONGWON KIM ,  MYUNG GIL KANG

IPC: H01L29/423 ,  H01L27/092 ,  H01L23/528 ,  H01L29/417

Abstract: Semiconductor devices and methods of forming the same are disclosed. The semiconductor devices may include a substrate including a first region and a second region, which are spaced apart from each other with a device isolation layer interposed therebetween, a first gate electrode and a second gate electrode on the first and second regions, respectively, an insulating separation pattern separating the first gate electrode and the second gate electrode from each other and extending in a second direction that traverses the first direction, a connection structure electrically connecting the first gate electrode to the second gate electrode, and a first signal line electrically connected to the connection structure. The first and second gate electrodes are extended in a first direction and are aligned to each other in the first direction. The first signal line may extend in the second direction and may vertically overlap the insulating separation pattern.

公开(公告)号：US20220278204A1

公开(公告)日：2022-09-01

申请号：US17742985

申请日：2022-05-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： ILGYOU SHIN ,  MINYI KIM ,  MYUNG GIL KANG ,  JINBUM KIM ,  SEUNG HUN LEE ,  KEUN HWI CHO

IPC: H01L29/15 ,  H01L29/78 ,  H01L29/417 ,  H01L29/10

Abstract: A semiconductor device includes; a substrate including a first region and a second region, a first active pattern extending upward from the first region, a first superlattice pattern on the first active pattern, a first active fin centrally disposed on the first active pattern, a first gate electrode disposed on the first active fin, and first source/drain patterns disposed on opposing sides of the first active fin and on the first active pattern. The first superlattice pattern includes at least one first semiconductor layer and at least one first blocker-containing layer, and the first blocker-containing layer includes at least one of oxygen, carbon, fluorine and nitrogen.

公开(公告)号：US20180114731A1

公开(公告)日：2018-04-26

申请号：US15838665

申请日：2017-12-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SOO YEON JEONG ,  MYUNG GIL KANG

IPC: H01L21/8238 ,  H01L29/49 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L29/06 ,  H01L27/092 ,  H01L23/535

CPC classification number: H01L21/823821 ,  H01L21/823828 ,  H01L21/823885 ,  H01L23/535 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/4966 ,  H01L29/66553 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/7827 ,  H01L29/785

Abstract: A vertical fin field effect transistor (V-FinFET) is provided as follows. A substrate has a lower source/drain (S/D). A fin structure extends vertically from an upper surface of the lower S/D. The fin structure includes a sidewall having an upper sidewall portion, a lower sidewall portion and a center sidewall portion positioned therebetween. An upper S/D is disposed on an upper surface of the fin structure. An upper spacer is disposed on the upper sidewall portion. A lower spacer is disposed on the lower sidewall portion. A stacked structure including a gate oxide layer and a first gate electrode is disposed on an upper surface of the lower spacer, the center sidewall portion and a lower surface of the upper spacer. A second gate electrode is disposed on the first gate electrode.

公开(公告)号：US20160181366A1

公开(公告)日：2016-06-23

申请号：US14980134

申请日：2015-12-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： CHANGWOO OH ,  MYUNG GIL KANG ,  BOMSOO KIM ,  JONGSHIK YOON

IPC: H01L29/10 ,  H01L27/088 ,  H01L29/423 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/1041 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/063 ,  H01L29/0649 ,  H01L29/0676 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/785

Abstract: Field effect transistors are provided. According to the field effect transistor, a source region and a drain region are provided on a substrate and a fin portion is provided to protrude from the substrate. The fin portion connects the source region and the drain region to each other. A gate electrode pattern is disposed on the fin portion and extends to cross over the fin portion. A gate dielectric layer is disposed between the fin portion and the gate electrode pattern. A semiconductor layer is disposed between the fin portion and the gate dielectric layer. The semiconductor layer and the fin portion have dopant-concentrations different from each other, respectively.

Abstract translation: 提供场效应晶体管。 根据场效应晶体管，源极区域和漏极区域设置在基板上，并且翅片部分设置成从基板突出。 翅片部分将源极区域和漏极区域彼此连接。 栅极电极图案设置在翅片部分上并且延伸以跨越翅片部分。 栅极介电层设置在鳍部与栅电极图案之间。 半导体层设置在翅片部分和栅极电介质层之间。 半导体层和鳍部分别具有彼此不同的掺杂剂浓度。

公开(公告)号：US20250072053A1

公开(公告)日：2025-02-27

申请号：US18947664

申请日：2024-11-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： MYUNG GIL KANG ,  DONG WON KIM ,  WOO SEOK PARK ,  KEUN HWI CHO ,  SUNG GI HUR

IPC: H01L29/423 ,  H01L27/092 ,  H01L29/06 ,  H01L29/786

Abstract: Semiconductor devices include a first active pattern including a first lower pattern extending in a first direction and a first sheet pattern spaced apart from the first lower pattern; and a first gate electrode on the first lower pattern, the first gate electrode extending in a second direction and surrounding the first sheet pattern, wherein the first lower pattern includes a first sidewall and a second sidewall opposite to each other, each of the first sidewall of the first lower pattern and the second sidewall of the first lower pattern extends in the first direction, the first gate electrode overlaps the first sidewall of the first lower pattern in the second direction by a first depth, the first gate electrode overlaps the second sidewall of the first lower pattern in the second direction by a second depth, and the first depth is different from the second depth.

公开(公告)号：US20250056861A1

公开(公告)日：2025-02-13

申请号：US18583006

申请日：2024-02-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： SOOJIN JEONG ,  MYUNG GIL KANG ,  DONGWON KIM ,  BEOMJIN PARK ,  DONGSUK SHIN ,  HYUN-KWAN YU ,  WOOSUK CHOI ,  SEUNGPYO HONG

IPC: H01L29/66 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device includes a substrate including an active pattern, a channel pattern on the active pattern, the channel pattern including a plurality of semiconductor patterns that are spaced apart from each other, a source/drain pattern electrically connected to the plurality of semiconductor patterns, an inner gate electrode between adjacent first and second semiconductor patterns of the plurality of semiconductor patterns, an inner gate insulating layer between the inner gate electrode and the first and second semiconductor patterns, an inner high-k dielectric layer between the inner gate electrode and the inner gate insulating layer, and an inner spacer between the inner gate insulating layer and the source/drain pattern. As the inner gate insulating layer includes an inner gate spacer, the inner gate electrode may stably fill the inner gate space. As a result, the electrical characteristics of the semiconductor device may be improved.

公开(公告)号：US20230387237A1

公开(公告)日：2023-11-30

申请号：US18449734

申请日：2023-08-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： MYUNG GIL KANG ,  Dong Won Kim ,  Woo Seok Park ,  Keun Hwi Cho ,  Sung Gi Hur

IPC: H01L29/423 ,  H01L27/092 ,  H01L29/06 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/78696 ,  H01L29/4236

Abstract: Semiconductor devices include a first active pattern including a first lower pattern extending in a first direction and a first sheet pattern spaced apart from the first lower pattern; and a first gate electrode on the first lower pattern, the first gate electrode extending in a second direction and surrounding the first sheet pattern, wherein the first lower pattern includes a first sidewall and a second sidewall opposite to each other, each of the first sidewall of the first lower pattern and the second sidewall of the first lower pattern extends in the first direction, the first gate electrode overlaps the first sidewall of the first lower pattern in the second direction by a first depth, the first gate electrode overlaps the second sidewall of the first lower pattern in the second direction by a second depth, and the first depth is different from the second depth.

公开(公告)号：US20190355822A1

公开(公告)日：2019-11-21

申请号：US16275675

申请日：2019-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： YOUNG CHAI JUNG ,  MYUNG GIL KANG ,  KANG ILL SEO ,  SEON BAE KIM ,  YONG HEE PARK

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/45 ,  H01L29/66 ,  H01L23/522

Abstract: VFET devices are provided. A VFET device includes a substrate including first and second protruding portions. The VFET device includes an isolation region between the first and second protruding portions. The VFET device includes first and second silicide regions on the first and second protruding portions, respectively. Moreover, the VFET device includes a contact on the first and second silicide regions. Related methods of forming a VFET device are also provided.

公开(公告)号：US20230112528A1

公开(公告)日：2023-04-13

申请号：US18046518

申请日：2022-10-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： MYUNG GIL KANG ,  Dong Won KIM ,  Woo Seok PARK ,  Keun Hwi CHO ,  Sung Gi HUR

IPC: H01L29/423 ,  H01L27/092 ,  H01L29/06 ,  H01L29/786

Abstract: Semiconductor devices include a first active pattern including a first lower pattern extending in a first direction and a first sheet pattern spaced apart from the first lower pattern; and a first gate electrode on the first lower pattern, the first gate electrode extending in a second direction different from the first direction and surrounding the first sheet pattern, wherein the first lower pattern includes a first sidewall and a second sidewall opposite to each other, each of the first sidewall of the first lower pattern and the second sidewall of the first lower pattern extends in the first direction, the first gate electrode overlaps the first sidewall of the first lower pattern in the second direction by a first depth, the first gate electrode overlaps the second sidewall of the first lower pattern in the second direction by a second depth, and the first depth is different from the second depth.

公开(公告)号：US20220037495A1

公开(公告)日：2022-02-03

申请号：US17209290

申请日：2021-03-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： MYUNG GIL KANG ,  DONG WON KIM ,  WOO SEOK PARK ,  KEUN HWI CHO ,  SUNG GI HUR

IPC: H01L29/423 ,  H01L27/092 ,  H01L29/786 ,  H01L29/06

Abstract: Semiconductor devices include a first active pattern including a first lower pattern extending in a first direction and a first sheet pattern spaced apart from the first lower pattern; and a first gate electrode on the first lower pattern, the first gate electrode extending in a second direction different from the first direction and surrounding the first sheet pattern, wherein the first lower pattern includes a first sidewall and a second sidewall opposite to each other, each of the first sidewall of the first lower pattern and the second sidewall of the first lower pattern extends in the first direction, the first gate electrode overlaps the first sidewall of the first lower pattern in the second direction by a first depth, the first gate electrode overlaps the second sidewall of the first lower pattern in the second direction by a second depth, and the first depth is different from the second depth.