公开(公告)号：US11778811B2

公开(公告)日：2023-10-03

申请号：US17555829

申请日：2021-12-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongjun Lee ,  Sang Chui Shin ,  Bong-Soo Kim ,  Jiyoung Kim

IPC: H10B12/00 ,  G11C5/06 ,  H01L21/768 ,  H01L23/528

CPC classification number: H10B12/482 ,  G11C5/063 ,  H01L21/7682 ,  H01L23/5283 ,  H10B12/02 ,  H10B12/0335 ,  H10B12/053 ,  H10B12/30 ,  H10B12/315 ,  H10B12/485 ,  H10B12/488 ,  H01L21/76897

Abstract: A semiconductor memory device may include a substrate, a bit line structure extending in one direction on the substrate, the bit line structure including a sidewall, a storage node contact on the sidewall of the bit line structure, first and second spacers between the sidewall of the bit line structure and the storage node contact, the first spacer separated from the second spacer by a space between the first spacer and the second spacer, an interlayer dielectric layer on the bit line structure, the interlayer dielectric layer including a bottom surface, a spacer capping pattern extending downward from the bottom surface of the interlayer dielectric layer toward the space between the first and second spacers, and a landing pad structure penetrating the interlayer dielectric layer, the landing pad structure coupled to the storage node contact.