公开(公告)号：US20170110576A1

公开(公告)日：2017-04-20

申请号：US15290240

申请日：2016-10-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Soo KIM ,  Gi-Gwan PARK ,  Sang-Koo KANG ,  Koung-Min RYU ,  Jae-Hoon LEE ,  Tae-Won HA

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/40 ,  H01L29/423 ,  H01L29/51

CPC classification number: H01L29/7831 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/513 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/7843 ,  H01L29/785 ,  H01L29/7854

Abstract: A semiconductor device capable of adjusting profiles of a gate electrode and a gate spacer by implanting or doping an element semiconductor material into an interlayer insulating layer may be provided. The semiconductor device may include a gate spacer on a substrate, the gate spacer defining a trench, a gate electrode filling the trench, and an interlayer insulating layer on the substrate, which surrounds the gate spacer, and at least a portion of which includes germanium.

公开(公告)号：US20170117192A1

公开(公告)日：2017-04-27

申请号：US15215951

申请日：2016-07-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-Ki Min ,  Gi-Gwan PARK ,  Sang-Koo KANG ,  Sung-Sao KIM ,  Ju-Youn KIM ,  Koung-Min RYU ,  Jae-Hoon LEE ,  Tae-Won HA

IPC: H01L21/8238 ,  H01L29/78 ,  H01L27/092

CPC classification number: H01L21/823864 ,  H01L21/28114 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/82385 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/42376 ,  H01L29/7854

Abstract: A semiconductor device may include a first gate electrode being formed on a substrate and having a first ratio of a width of an upper surface to a width of a lower surface, a second gate electrode being formed on the substrate and having a second ratio of the width of the upper surface to the width of the lower surface, wherein the second ratio is less than the first ratio, a first gate spacer being formed on a sidewall of the first gate electrode, a second gate spacer being formed on a sidewall of the second gate electrode and an interlayer insulating film covering the first gate spacer and the second gate spacer.

公开(公告)号：US20190088779A1

公开(公告)日：2019-03-21

申请号：US16193521

申请日：2018-11-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Soo KIM ,  Gi-Gwan PARK ,  Sang-Koo KANG ,  Koung-Min RYU ,  Jae-Hoon LEE ,  Tae-Won HA

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/7831 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/513 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/7843 ,  H01L29/785 ,  H01L29/7854

Abstract: A semiconductor device capable of adjusting profiles of a gate electrode and a gate spacer by implanting or doping an element semiconductor material into an interlayer insulating layer may be provided. The semiconductor device may include a gate spacer on a substrate, the gate spacer defining a trench, a gate electrode filling the trench, and an interlayer insulating layer on the substrate, which surrounds the gate spacer, and at least a portion of which includes germanium.

公开(公告)号：US20170053913A1

公开(公告)日：2017-02-23

申请号：US15233123

申请日：2016-08-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-Ki MIN ,  Koung-Min RYU ,  Sang-Koo KANG

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/78

Abstract: There is provided a semiconductor device capable of adjusting profiles of a gate electrode and a gate spacer using a hybrid interlayer insulating film. The semiconductor device includes a gate electrode on a substrate, a gate spacer being on a sidewall of the gate electrode and including an upper portion and a lower portion, a lower interlayer insulating film being on the substrate and overlapping with the lower portion of the gate spacer, and an upper interlayer insulating film being on the lower interlayer insulating film and overlapping with the upper portion of the gate spacer, wherein the lower interlayer insulating film is not interposed between the upper interlayer insulating film and the upper portion of the gate spacer.

Abstract translation: 提供了能够使用混合层间绝缘膜来调整栅极电极和栅极间隔物的轮廓的半导体器件。 半导体器件包括在基板上的栅极电极，栅极间隔物位于栅电极的侧壁上并且包括上部和下部，下部层间绝缘膜位于衬底上并与栅极的下部重叠 间隔物和上层间绝缘膜，位于下层间绝缘膜上并与栅极间隔物的上部重叠，其中下层间绝缘膜不夹在上层间绝缘膜和栅间隔物的上部之间。