公开(公告)号：US20160379976A1

公开(公告)日：2016-12-29

申请号：US15012920

申请日：2016-02-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Youn KIM

IPC: H01L27/088 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848

Abstract: A semiconductor device is provided. The semiconductor device includes a first fin-type pattern and a second fin-type pattern formed abreast in a lengthwise direction, a first trench formed between the first fin-type pattern and the second fin-type pattern, a field insulating film partially filling the first trench, an interlayer insulating film on the field insulating film, an insulating line pattern, and a conductive pattern. An upper surface of the field insulating film is lower than an upper surface of the first fin-type pattern and an upper surface of the second fin-type pattern. The interlayer insulating film covers the first fin-type pattern and the second fin-type pattern, and includes a second trench exposing the upper surface of the field insulating film. The second trench includes an upper portion and a lower portion. The insulating line pattern fills the lower portion of the second trench, and the conductive pattern fills the upper portion of the second trench.

Abstract translation: 提供半导体器件。 半导体器件包括在长度方向上并排形成的第一鳍式图案和第二鳍片图案，形成在第一鳍片型图案和第二鳍片型图案之间的第一沟槽，场绝缘膜部分地填充 第一沟槽，场绝缘膜上的层间绝缘膜，绝缘线图案和导电图案。 场绝缘膜的上表面低于第一鳍式图案的上表面和第二鳍片型图案的上表面。 层间绝缘膜覆盖第一鳍状图案和第二鳍状图案，并且包括暴露场绝缘膜的上表面的第二沟槽。 第二沟槽包括上部和下部。 绝缘线图案填充第二沟槽的下部，并且导电图案填充第二沟槽的上部。

公开(公告)号：US20130295758A1

公开(公告)日：2013-11-07

申请号：US13720435

申请日：2012-12-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-Youn KIM

IPC: H01L21/8238

CPC classification number: H01L27/0922 ,  H01L21/823842 ,  H01L21/823885 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4916 ,  H01L29/4966

Abstract: A method of manufacturing a semiconductor device comprises forming an interlayer insulating film on a semiconductor substrate, the interlayer insulating film including a trench, forming a work function metal layer in the trench, forming an insulating film on the work function metal layer, forming a sacrificial film on the insulating film and filling the trench, forming a sacrificial film pattern with a top surface disposed in the trench by etching the sacrificial film, forming an insulating film pattern by selectively etching a portion of the insulating film which is formed higher than the sacrificial film pattern, and forming a work function metal pattern with a top surface disposed in the trench by selectively etching a portion of the work function metal layer which is formed higher than the insulating film pattern.

公开(公告)号：US20140361380A1

公开(公告)日：2014-12-11

申请号：US14469013

申请日：2014-08-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-Youn KIM

IPC: H01L27/092 ,  H01L29/10 ,  H01L29/49 ,  H01L27/088 ,  H01L29/423

CPC classification number: H01L27/0922 ,  H01L21/823842 ,  H01L21/823885 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4916 ,  H01L29/4966

Abstract: A method of manufacturing a semiconductor device comprises forming an interlayer insulating film on a semiconductor substrate, the interlayer insulating film including a trench, forming a work function metal layer in the trench, forming an insulating film on the work function metal layer, forming a sacrificial film on the insulating film and filling the trench, forming a sacrificial film pattern with a top surface disposed in the trench by etching the sacrificial film, forming an insulating film pattern by selectively etching a portion of the insulating film which is formed higher than the sacrificial film pattern, and forming a work function metal pattern with a top surface disposed in the trench by selectively etching a portion of the work function metal layer which is formed higher than the insulating film pattern.

Abstract translation: 一种制造半导体器件的方法包括在半导体衬底上形成层间绝缘膜，所述层间绝缘膜包括沟槽，在沟槽中形成功函数金属层，在功函数金属层上形成绝缘膜，形成牺牲层 在绝缘膜上填充并填充沟槽，通过蚀刻牺牲膜形成具有设置在沟槽中的顶表面的牺牲膜图案，通过选择性地蚀刻形成为高于牺牲膜的绝缘膜的一部分来形成绝缘膜图案 并且通过选择性地蚀刻形成在绝缘膜图案之上的功函数金属层的一部分，形成具有设置在沟槽中的顶表面的功函数金属图案。

公开(公告)号：US20180233507A1

公开(公告)日：2018-08-16

申请号：US15950313

申请日：2018-04-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-Youn KIM

IPC: H01L27/11 ,  H01L21/8238 ,  H01L29/49 ,  H01L21/3213 ,  H01L29/66 ,  H01L27/108 ,  H01L29/423 ,  H01L27/092 ,  H01L29/51 ,  H01L21/8234

CPC classification number: H01L27/1104 ,  G11C11/412 ,  H01L21/02304 ,  H01L21/02323 ,  H01L21/02362 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/32134 ,  H01L21/32139 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823878 ,  H01L27/0207 ,  H01L27/0617 ,  H01L27/0705 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/108 ,  H01L27/1116 ,  H01L29/401 ,  H01L29/408 ,  H01L29/42364 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

Abstract: A semiconductor device includes first through fourth areas, first through fourth gate stacks, the first gate stack includes a first high-dielectric layer, a first TiN layer to contact the first high-dielectric layer, and a first gate metal on the first TiN layer, the second gate stack includes a second high-dielectric layer, a second TiN layer to contact the second high-dielectric layer, and a second gate metal on the second TiN layer, the third gate stack includes a third high-dielectric layer, a third TiN layer to contact the third high-dielectric layer, and a third gate metal on the third TiN layer, and the fourth gate stack includes a fourth high-dielectric layer, a fourth TiN layer to contact the fourth high-dielectric layer, and a fourth gate metal on the fourth TiN layer, the first through fourth thicknesses of the TiN layers being different.

公开(公告)号：US20170069634A1

公开(公告)日：2017-03-09

申请号：US15354271

申请日：2016-11-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-Youn KIM

IPC: H01L27/11 ,  H01L27/092 ,  H01L21/3213 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/51 ,  H01L29/49 ,  H01L29/423

CPC classification number: H01L27/1104 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/32136 ,  H01L21/32139 ,  H01L21/82345 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/108 ,  H01L27/1116 ,  H01L29/42364 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: A semiconductor device includes first through fourth areas, first through fourth gate stacks, the first gate stack includes a first high-dielectric layer, a first TiN layer to contact the first high-dielectric layer, and a first gate metal on the first TiN layer, the second gate stack includes a second high-dielectric layer, a second TiN layer to contact the second high-dielectric layer, and a second gate metal on the second TiN layer, the third gate stack includes a third high-dielectric layer, a third TiN layer to contact the third high-dielectric layer, and a third gate metal on the third TiN layer, and the fourth gate stack includes a fourth high-dielectric layer, a fourth TiN layer to contact the fourth high-dielectric layer, and a fourth gate metal on the fourth TiN layer, the first through fourth thicknesses of the TiN layers being different.

Abstract translation: 半导体器件包括第一至第四区域，第一至第四栅极堆叠，第一栅极堆叠包括第一高电介质层，与第一高电介质层接触的第一TiN层和第一TiN层上的第一栅极金属 所述第二栅叠层包括第二高电介质层，与所述第二高电介质层接触的第二TiN层和所述第二TiN层上的第二栅极金属，所述第三栅叠层包括第三高电介质层， 第三TiN层与第三高电介质层接触，第三栅极金属在第三TiN层上，第四栅叠层包括第四高电介质层，与第四高电介质层接触的第四TiN层，以及 在第四TiN层上的第四栅极金属，TiN层的第一至第四厚度不同。

公开(公告)号：US20150325670A1

公开(公告)日：2015-11-12

申请号：US14728018

申请日：2015-06-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Youn KIM ,  Young-Hun KIM

IPC: H01L29/51 ,  H01L21/28 ,  H01L29/49

CPC classification number: H01L29/517 ,  H01L21/02 ,  H01L21/28088 ,  H01L21/28167 ,  H01L21/28194 ,  H01L21/823857 ,  H01L27/088 ,  H01L27/092 ,  H01L27/1104 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/78

Abstract: A semiconductor device having high-k gate insulation films and a method of fabricating the semiconductor device are provided. The semiconductor device includes a first gate insulation film on a substrate and the first gate insulation film includes a material selected from the group consisting of HfO2, ZrO2, Ta2O5, TiO2, SrTiO3 and (Ba,Sr)TiO3, and lanthanum (La). Additionally, the semiconductor device includes a first barrier film on the first gate insulation film, a first gate electrode on the first barrier film, and n-type source/drain regions in the substrate at both sides of the first gate electrode.

Abstract translation: 提供了具有高k栅极绝缘膜的半导体器件和制造半导体器件的方法。 半导体器件包括在衬底上的第一栅极绝缘膜，第一栅极绝缘膜包括选自HfO 2，ZrO 2，Ta 2 O 5，TiO 2，SrTiO 3和（Ba，Sr）TiO 3和镧（La）的材料。 此外，半导体器件包括第一栅极绝缘膜上的第一阻挡膜，第一阻挡膜上的第一栅极电极和第一栅电极两侧的基板中的n型源极/漏极区域。

公开(公告)号：US20150179642A1

公开(公告)日：2015-06-25

申请号：US14633280

申请日：2015-02-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-Youn KIM

IPC: H01L27/088 ,  H01L29/423 ,  H01L27/092

CPC classification number: H01L27/0922 ,  H01L21/823842 ,  H01L21/823885 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4916 ,  H01L29/4966

Abstract: A method of manufacturing a semiconductor device comprises forming an interlayer insulating film on a semiconductor substrate, the interlayer insulating film including a trench, forming a work function metal layer in the trench, forming an insulating film on the work function metal layer, forming a sacrificial film on the insulating film and filling the trench, forming a sacrificial film pattern with a top surface disposed in the trench by etching the sacrificial film, forming an insulating film pattern by selectively etching a portion of the insulating film which is formed higher than the sacrificial film pattern, and forming a work function metal pattern with a top surface disposed in the trench by selectively etching a portion of the work function metal layer which is formed higher than the insulating film pattern.

Abstract translation: 一种制造半导体器件的方法包括在半导体衬底上形成层间绝缘膜，所述层间绝缘膜包括沟槽，在沟槽中形成功函数金属层，在功函数金属层上形成绝缘膜，形成牺牲层 在绝缘膜上填充并填充沟槽，通过蚀刻牺牲膜形成具有设置在沟槽中的顶表面的牺牲膜图案，通过选择性地蚀刻形成为高于牺牲膜的绝缘膜的一部分来形成绝缘膜图案 并且通过选择性地蚀刻形成在绝缘膜图案之上的功函数金属层的一部分，形成具有设置在沟槽中的顶表面的功函数金属图案。

公开(公告)号：US20140103403A1

公开(公告)日：2014-04-17

申请号：US13650784

申请日：2012-10-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-Youn KIM ,  Je-Don KIM

IPC: H01L21/283 ,  H01L29/78

CPC classification number: H01L27/092 ,  H01L21/28247 ,  H01L21/76801 ,  H01L21/76829 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/82345 ,  H01L21/823475 ,  H01L29/42364 ,  H01L29/42372 ,  H01L29/66545

Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming an insulation film including a trench on a substrate, forming a first metal gate film pattern along side and bottom surfaces of the trench, forming a second metal gate film on the first metal gate film pattern and the insulation film, and forming a second metal gate film pattern positioned on the first metal gate film pattern by removing the second metal gate film to expose at least a portion of the insulation film and forming a blocking layer pattern on the second metal gate film pattern by oxidizing an exposed surface of the second metal gate film pattern.

Abstract translation: 提供一种制造半导体器件的方法。 该方法包括在衬底上形成包括沟槽的绝缘膜，沿沟槽的侧面和底面形成第一金属栅极膜图案，在第一金属栅极膜图案和绝缘膜上形成第二金属栅极膜，并形成 第二金属栅膜膜图案，其通过去除所述第二金属栅极膜以暴露所述绝缘膜的至少一部分并且在所述第二金属栅膜膜图案上形成阻挡层图案而定位在所述第一金属栅膜膜图案上， 第二金属栅膜图案。

公开(公告)号：US20170117192A1

公开(公告)日：2017-04-27

申请号：US15215951

申请日：2016-07-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-Ki Min ,  Gi-Gwan PARK ,  Sang-Koo KANG ,  Sung-Sao KIM ,  Ju-Youn KIM ,  Koung-Min RYU ,  Jae-Hoon LEE ,  Tae-Won HA

IPC: H01L21/8238 ,  H01L29/78 ,  H01L27/092

CPC classification number: H01L21/823864 ,  H01L21/28114 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/82385 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/42376 ,  H01L29/7854

Abstract: A semiconductor device may include a first gate electrode being formed on a substrate and having a first ratio of a width of an upper surface to a width of a lower surface, a second gate electrode being formed on the substrate and having a second ratio of the width of the upper surface to the width of the lower surface, wherein the second ratio is less than the first ratio, a first gate spacer being formed on a sidewall of the first gate electrode, a second gate spacer being formed on a sidewall of the second gate electrode and an interlayer insulating film covering the first gate spacer and the second gate spacer.

公开(公告)号：US20160372467A1

公开(公告)日：2016-12-22

申请号：US15014291

申请日：2016-02-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-Youn KIM ,  Hyun-Jo KIM ,  Hwa-Sung RHEE

IPC: H01L27/088 ,  H01L29/06 ,  H01L27/02

CPC classification number: H01L27/0886 ,  H01L27/0207 ,  H01L29/0649

Abstract: Semiconductor devices are provided. The semiconductor device includes an active fin which extends along a first direction and has a protruding shape, a gate structure which is disposed on the active fin to extend along a second direction intersecting the first direction, and a spacer which is disposed on at least one side of the gate structure, wherein the gate structure includes a first area and a second area which is adjacent to the first area in the second direction, wherein a first width of the first area in the first direction is different from a second width of the second area in the first direction, and the spacer extends continuously along both the first area and the second area.

Abstract translation: 提供半导体器件。 该半导体器件包括沿着第一方向延伸并具有突出形状的有源鳍片，设置在有源鳍片上以沿与第一方向相交的第二方向延伸的栅极结构，以及设置在至少一个 所述栅极结构包括第一区域和与所述第二方向上的所述第一区域相邻的第二区域，其中，所述第一方向上的所述第一区域的第一宽度不同于所述第一区域的第二宽度， 第二区域沿着第一方向延伸，并且间隔件沿着第一区域和第二区域连续地延伸。