公开(公告)号：US20170110576A1

公开(公告)日：2017-04-20

申请号：US15290240

申请日：2016-10-11

申请人： Samsung Electronics Co., Ltd.

发明人： Sung-Soo KIM ,  Gi-Gwan PARK ,  Sang-Koo KANG ,  Koung-Min RYU ,  Jae-Hoon LEE ,  Tae-Won HA

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/40 ,  H01L29/423 ,  H01L29/51

CPC分类号： H01L29/7831 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/513 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/7843 ,  H01L29/785 ,  H01L29/7854

摘要： A semiconductor device capable of adjusting profiles of a gate electrode and a gate spacer by implanting or doping an element semiconductor material into an interlayer insulating layer may be provided. The semiconductor device may include a gate spacer on a substrate, the gate spacer defining a trench, a gate electrode filling the trench, and an interlayer insulating layer on the substrate, which surrounds the gate spacer, and at least a portion of which includes germanium.

公开(公告)号：US20180190821A1

公开(公告)日：2018-07-05

申请号：US15889803

申请日：2018-02-06

申请人： Samsung Electronics Co., Ltd.

发明人： Sung-Soo KIM ,  Gi-Gwan PARK ,  Song-E KIM ,  Koung-Min RYU ,  Sun-Ki MIN

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/417

CPC分类号： H01L29/7855 ,  H01L29/0657 ,  H01L29/41791 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/7853 ,  H01L29/7854

摘要： A semiconductor device is provided which includes a first fin-type pattern including a first side surface and a second side surface opposite to each other, a first trench of a first depth adjacent to the first side surface, a second trench of a second depth adjacent to the second side surface. The second depth differs from the first depth, and a first field insulating film partially fills the first trench and a second field insulating film partially fills the second trench. The first fin-type pattern has a lower portion, and an upper portion having a narrower width than the lower portion, and has a first stepped portion on a boundary between the upper portion and the lower portion. The first field insulating film includes a first lower field insulating film in contact with the lower portion, and a first upper field insulating film in contact with the upper portion.

公开(公告)号：US20170117192A1

公开(公告)日：2017-04-27

申请号：US15215951

申请日：2016-07-21

申请人： Samsung Electronics Co., Ltd.

发明人： Sun-Ki Min ,  Gi-Gwan PARK ,  Sang-Koo KANG ,  Sung-Sao KIM ,  Ju-Youn KIM ,  Koung-Min RYU ,  Jae-Hoon LEE ,  Tae-Won HA

IPC分类号： H01L21/8238 ,  H01L29/78 ,  H01L27/092

CPC分类号： H01L21/823864 ,  H01L21/28114 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/82385 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/42376 ,  H01L29/7854

摘要： A semiconductor device may include a first gate electrode being formed on a substrate and having a first ratio of a width of an upper surface to a width of a lower surface, a second gate electrode being formed on the substrate and having a second ratio of the width of the upper surface to the width of the lower surface, wherein the second ratio is less than the first ratio, a first gate spacer being formed on a sidewall of the first gate electrode, a second gate spacer being formed on a sidewall of the second gate electrode and an interlayer insulating film covering the first gate spacer and the second gate spacer.

公开(公告)号：US20170040208A1

公开(公告)日：2017-02-09

申请号：US15142043

申请日：2016-04-29

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Seung-Hoon CHOI ,  Ho-Young KIM ,  Gi-Gwan PARK ,  Hyun-Kyung BAE ,  Bo-Un YOON ,  Il-Young YOON

IPC分类号： H01L21/768

CPC分类号： H01L21/7684 ,  B24B37/042 ,  H01L21/67219 ,  H01L21/76819 ,  H01L21/76849 ,  H01L21/76897 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L29/41791

摘要： A method of forming a plug and manufacturing a semiconductor device, a polishing chamber, and a semiconductor device, the method of forming a plug including forming an opening in an insulating interlayer pattern on a substrate; forming a metal layer to fill the opening; performing a first CMP process during a first time period until a top surface of the insulating interlayer pattern is exposed while pressing the substrate onto a first polishing pad to polish the metal layer; performing a second CMP process during a second time period while pressing the substrate onto a second polishing pad to polish the metal layer and the insulating interlayer pattern, so that a metal plug is formed in the insulating interlayer pattern; and performing a first cleaning process on the second polishing pad while keeping the substrate spaced apart from the second polishing pad on the second platen.

摘要翻译： 一种形成插头并制造半导体器件，抛光室和半导体器件的方法，包括在衬底上形成绝缘层间图案中的开口的形成插头的方法; 形成金属层以填充开口; 在第一时间段内执行第一CMP处理直到绝缘层间图案的顶表面暴露，同时将基板压在第一抛光垫上以抛光金属层; 在第二时间段内执行第二CMP处理，同时将衬底按压到第二抛光垫上以抛光金属层和绝缘层间图案，从而在绝缘层间图案中形成金属插塞; 以及在所述第二台板上保持与所述第二抛光垫间隔开的所述基板的同时对所述第二抛光垫进行第一清洁处理。

公开(公告)号：US20170200718A1

公开(公告)日：2017-07-13

申请号：US15384834

申请日：2016-12-20

申请人： Samsung Electronics Co., Ltd.

发明人： Sung-Hyun CHOI ,  Yong-Suk TAK ,  Gi-Gwan PARK ,  Bon-Young KOO ,  Ki-Yeon PARK ,  Won-Oh SEO

IPC分类号： H01L27/088 ,  H01L29/08 ,  H01L23/26 ,  H01L21/02 ,  H01L29/161 ,  H01L29/165 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L29/16

CPC分类号： H01L27/0886 ,  H01L21/02636 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L23/26 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/7851

摘要： A semiconductor device includes an active fin on a substrate, a gate structure on the active fin, a gate spacer structure on a sidewall of the gate structure, and a source/drain layer on at least a portion of the active fin adjacent the gate spacer structure. The gate spacer structure includes a wet etch stop pattern, an oxygen-containing silicon pattern, and an outgassing prevention pattern sequentially stacked.

公开(公告)号：US20170110569A1

公开(公告)日：2017-04-20

申请号：US15292144

申请日：2016-10-13

申请人： Samsung Electronics Co., Ltd.

发明人： Chong-Kwang CHANG ,  Young-Mook OH ,  Hak-Yoon AHN ,  Jung-Gun YOU ,  Gi-Gwan PARK ,  Baik-Min SUNG

IPC分类号： H01L29/78 ,  H01L23/528 ,  H01L21/768 ,  H01L23/522

CPC分类号： H01L29/785 ,  H01L21/76807 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53295 ,  H01L2029/7858

摘要： A semiconductor device includes a gate structure on a substrate, a source/drain layer on a portion of the substrate adjacent the gate structure, a first contact plug contacting an upper surface of the source/drain layer, and a second contact plug contacting upper surfaces of the gate structure and the first contact plug. A bottom surface of the second contact plug has a first portion not contacting the upper surface of the first contact plug, and the first portion is higher than the upper surface of the gate structure.

公开(公告)号：US20170103916A1

公开(公告)日：2017-04-13

申请号：US15182024

申请日：2016-06-14

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Yong-Ho JEON ,  Sang-Su KIM ,  Cheol KIM ,  Yong-Suk TAK ,  Myung-Geun SONG ,  Gi-Gwan PARK

IPC分类号： H01L21/768 ,  H01L29/08 ,  H01L29/161 ,  H01L29/16 ,  H01L29/49 ,  H01L29/78 ,  H01L23/535 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/092 ,  H01L29/165

CPC分类号： H01L21/76897 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823864 ,  H01L21/823871 ,  H01L23/535 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7848

摘要： A semiconductor device, including a first fin-type pattern; a first gate spacer on the first fin-type pattern, intersecting the first fin-type pattern, and including an upper portion and a lower portion; a second gate spacer on the first fin-type pattern, intersecting the first fin-type pattern, and being spaced apart from the first gate spacer; a first trench defined by the first gate spacer and the second gate spacer; a first gate electrode partially filling the first trench; a first capping pattern on the first gate electrode and filling the first trench; and an interlayer insulating layer covering an upper surface of the capping pattern, a width of the upper portion of the first gate spacer decreasing as a distance from an upper surface of the first fin-type pattern increases, and an outer sidewall of the upper portion of the first gate spacer contacting the interlayer insulating layer.

公开(公告)号：US20190088779A1

公开(公告)日：2019-03-21

申请号：US16193521

申请日：2018-11-16

申请人： Samsung Electronics Co., Ltd.

发明人： Sung-Soo KIM ,  Gi-Gwan PARK ,  Sang-Koo KANG ,  Koung-Min RYU ,  Jae-Hoon LEE ,  Tae-Won HA

IPC分类号： H01L29/78 ,  H01L29/40 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66

CPC分类号： H01L29/7831 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/513 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/7843 ,  H01L29/785 ,  H01L29/7854

摘要： A semiconductor device capable of adjusting profiles of a gate electrode and a gate spacer by implanting or doping an element semiconductor material into an interlayer insulating layer may be provided. The semiconductor device may include a gate spacer on a substrate, the gate spacer defining a trench, a gate electrode filling the trench, and an interlayer insulating layer on the substrate, which surrounds the gate spacer, and at least a portion of which includes germanium.

公开(公告)号：US20170317213A1

公开(公告)日：2017-11-02

申请号：US15410238

申请日：2017-01-19

申请人： Samsung Electronics Co., Ltd.

发明人： Mi-Seon PARK ,  Gi-Gwan PARK ,  Tae-Jong LEE ,  Yong-Suk TAK ,  Ki-Yeon PARK

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/02

CPC分类号： H01L29/7851 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/0228 ,  H01L29/0649 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

摘要： A semiconductor device includes an active fin on a substrate, a gate structure on the active fin, a gate spacer structure directly on a sidewall of the gate structure, and a source/drain layer on a portion of the active fin adjacent the gate spacer structure. The gate spacer structure includes a silicon oxycarbonitride (SiOCN) pattern and a silicon dioxide (SiO2) pattern sequentially stacked.