公开(公告)号：US20140167177A1

公开(公告)日：2014-06-19

申请号：US14081543

申请日：2013-11-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-Hun KIM ,  Ju-Youn KIM ,  Koung-Min RYU ,  Jong-Mil YOUN ,  Jong-Ho LEE

IPC: H01L27/11 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L27/1104 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/1029

Abstract: A semiconductor device includes a channel layer over an active region, first and second field regions adjacent the active region, and a gate structure over the channel layer and portions of the first and second field regions. The first and second field regions include grooves adjacent respective sidewalls of the channel layer, and bottom surfaces of the grooves are below a bottom surface of the channel layer.

Abstract translation: 半导体器件包括在有源区上的沟道层，与有源区相邻的第一和第二场区以及沟道层上的栅极结构以及第一和第二场区的部分。 第一和第二场区域包括与沟道层的相应侧壁相邻的沟槽，并且沟槽的底表面在沟道层的底表面下方。

公开(公告)号：US20180190821A1

公开(公告)日：2018-07-05

申请号：US15889803

申请日：2018-02-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Soo KIM ,  Gi-Gwan PARK ,  Song-E KIM ,  Koung-Min RYU ,  Sun-Ki MIN

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/417

CPC classification number: H01L29/7855 ,  H01L29/0657 ,  H01L29/41791 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/7853 ,  H01L29/7854

Abstract: A semiconductor device is provided which includes a first fin-type pattern including a first side surface and a second side surface opposite to each other, a first trench of a first depth adjacent to the first side surface, a second trench of a second depth adjacent to the second side surface. The second depth differs from the first depth, and a first field insulating film partially fills the first trench and a second field insulating film partially fills the second trench. The first fin-type pattern has a lower portion, and an upper portion having a narrower width than the lower portion, and has a first stepped portion on a boundary between the upper portion and the lower portion. The first field insulating film includes a first lower field insulating film in contact with the lower portion, and a first upper field insulating film in contact with the upper portion.

公开(公告)号：US20190096673A1

公开(公告)日：2019-03-28

申请号：US16052063

申请日：2018-08-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEUNG-HEON LEE ,  Koung-Min RYU ,  Kyung-Seok OH ,  Sang-Jin HYUN

IPC: H01L21/033 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/67 ,  H01L21/02 ,  H01J37/32 ,  C23C16/50 ,  C23C16/24

Abstract: Disclosed are an apparatus for forming a layer and a method of forming the layer using the same. The apparatus includes a transfer chamber in which a substrate is transferred, a deposition chamber positioned at a side of the transfer chamber and performing a deposition process on the substrate to thereby form the layer on the substrate, and at least a de-hydrogen chamber positioned at another side of the transfer chamber and performing a de-hydrogen process on the layer on the substrate to reduce a hydrogen concentration in the layer. Accordingly, the de-hydrogen process is performed in the apparatus without unloading of the substrate from the apparatus.

公开(公告)号：US20170110576A1

公开(公告)日：2017-04-20

申请号：US15290240

申请日：2016-10-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Soo KIM ,  Gi-Gwan PARK ,  Sang-Koo KANG ,  Koung-Min RYU ,  Jae-Hoon LEE ,  Tae-Won HA

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/40 ,  H01L29/423 ,  H01L29/51

CPC classification number: H01L29/7831 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/513 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/7843 ,  H01L29/785 ,  H01L29/7854

Abstract: A semiconductor device capable of adjusting profiles of a gate electrode and a gate spacer by implanting or doping an element semiconductor material into an interlayer insulating layer may be provided. The semiconductor device may include a gate spacer on a substrate, the gate spacer defining a trench, a gate electrode filling the trench, and an interlayer insulating layer on the substrate, which surrounds the gate spacer, and at least a portion of which includes germanium.

公开(公告)号：US20190088779A1

公开(公告)日：2019-03-21

申请号：US16193521

申请日：2018-11-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Soo KIM ,  Gi-Gwan PARK ,  Sang-Koo KANG ,  Koung-Min RYU ,  Jae-Hoon LEE ,  Tae-Won HA

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/7831 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/513 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/7843 ,  H01L29/785 ,  H01L29/7854

Abstract: A semiconductor device capable of adjusting profiles of a gate electrode and a gate spacer by implanting or doping an element semiconductor material into an interlayer insulating layer may be provided. The semiconductor device may include a gate spacer on a substrate, the gate spacer defining a trench, a gate electrode filling the trench, and an interlayer insulating layer on the substrate, which surrounds the gate spacer, and at least a portion of which includes germanium.

公开(公告)号：US20170053913A1

公开(公告)日：2017-02-23

申请号：US15233123

申请日：2016-08-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-Ki MIN ,  Koung-Min RYU ,  Sang-Koo KANG

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/78

Abstract: There is provided a semiconductor device capable of adjusting profiles of a gate electrode and a gate spacer using a hybrid interlayer insulating film. The semiconductor device includes a gate electrode on a substrate, a gate spacer being on a sidewall of the gate electrode and including an upper portion and a lower portion, a lower interlayer insulating film being on the substrate and overlapping with the lower portion of the gate spacer, and an upper interlayer insulating film being on the lower interlayer insulating film and overlapping with the upper portion of the gate spacer, wherein the lower interlayer insulating film is not interposed between the upper interlayer insulating film and the upper portion of the gate spacer.

Abstract translation: 提供了能够使用混合层间绝缘膜来调整栅极电极和栅极间隔物的轮廓的半导体器件。 半导体器件包括在基板上的栅极电极，栅极间隔物位于栅电极的侧壁上并且包括上部和下部，下部层间绝缘膜位于衬底上并与栅极的下部重叠 间隔物和上层间绝缘膜，位于下层间绝缘膜上并与栅极间隔物的上部重叠，其中下层间绝缘膜不夹在上层间绝缘膜和栅间隔物的上部之间。

公开(公告)号：US20180102429A1

公开(公告)日：2018-04-12

申请号：US15812527

申请日：2017-11-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-soo KIM ,  Song-E KIM ,  Koung-Min RYU ,  Sun-Ki Min

IPC: H01L29/78 ,  H01L27/12 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L27/1233 ,  H01L29/66795 ,  H01L29/7846 ,  H01L29/7854

Abstract: A semiconductor device is provided that includes a deep trench defining an active region, and a fin-type pattern protruding within the active region. The fin-type pattern having a lower portion, an upper portion of a narrower width than the lower portion, and a first stepped portion formed at a boundary between the upper portion and the lower portion. The device also includes a first field insulating film surrounding the lower portion and a second field insulating film formed on the first field insulating film and partially surrounding the upper portion.

公开(公告)号：US20170117192A1

公开(公告)日：2017-04-27

申请号：US15215951

申请日：2016-07-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-Ki Min ,  Gi-Gwan PARK ,  Sang-Koo KANG ,  Sung-Sao KIM ,  Ju-Youn KIM ,  Koung-Min RYU ,  Jae-Hoon LEE ,  Tae-Won HA

IPC: H01L21/8238 ,  H01L29/78 ,  H01L27/092

CPC classification number: H01L21/823864 ,  H01L21/28114 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/82385 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/42376 ,  H01L29/7854

Abstract: A semiconductor device may include a first gate electrode being formed on a substrate and having a first ratio of a width of an upper surface to a width of a lower surface, a second gate electrode being formed on the substrate and having a second ratio of the width of the upper surface to the width of the lower surface, wherein the second ratio is less than the first ratio, a first gate spacer being formed on a sidewall of the first gate electrode, a second gate spacer being formed on a sidewall of the second gate electrode and an interlayer insulating film covering the first gate spacer and the second gate spacer.

公开(公告)号：US20170054020A1

公开(公告)日：2017-02-23

申请号：US15189960

申请日：2016-06-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-soo KIM ,  Koung-Min RYU ,  Sun-Ki Min

IPC: H01L29/78 ,  H01L29/06 ,  H01L23/535

CPC classification number: H01L29/785 ,  H01L27/1233 ,  H01L29/66795 ,  H01L29/7846 ,  H01L29/7854

Abstract: A semiconductor device is provided that includes a deep trench defining an active region, and a fin-type pattern protruding within the active region. The fin-type pattern having a lower portion, an upper portion of a narrower width than the lower portion, and a first stepped portion formed at a boundary between the upper portion and the lower portion. The device also includes a first field insulating film surrounding the lower portion and a second field insulating film formed on the first field insulating film and partially surrounding the upper portion.

Abstract translation: 提供一种半导体器件，其包括限定有源区的深沟槽和在有源区域内突出的鳍型图案。 翅片型图案具有下部，比下部更窄的上部，以及形成在上部和下部之间的边界处的第一阶梯部。 该器件还包括围绕下部的第一场绝缘膜和形成在第一场绝缘膜上并部分围绕上部的第二场绝缘膜。