公开(公告)号：US20170133367A1

公开(公告)日：2017-05-11

申请号：US15416016

申请日：2017-01-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Hoon BAEK ,  Sun-Young PARK ,  Sang-Kyu OH ,  Ha-Young KIM ,  Jung-Ho DO ,  Moo-Gyu BAE ,  Seung-Young LEE

IPC: H01L27/088 ,  H01L21/8234 ,  H01L27/11 ,  H01L23/528 ,  H01L27/02

CPC classification number: H01L27/088 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/1104

Abstract: Systems on chips are provided. A system on chip (SoC) includes a first gate line, a second gate line and a third gate line extending in a first direction, a gate isolation region cutting the first gate line, the second gate line and the third gate line and extending in a second direction across the first direction, a first gate contact formed on the second gate line arranged between the first gate line and the third gate line, and electrically connecting the cut second gate line, a second gate contact formed on the first gate line, a third gate contact formed on the third gate line, a first metal line electrically connecting the second gate contact and the third gate contact, and a second metal line electrically connected to the first gate contact.

公开(公告)号：US20180342505A1

公开(公告)日：2018-11-29

申请号：US16037581

申请日：2018-07-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Hoon BAEK ,  Sun-Young PARK ,  Sang-Kyu OH ,  Ha-young KIM ,  Jung-Ho DO ,  Moo-Gyu BAE ,  Seung-Young LEE

IPC: H01L27/088 ,  H01L23/528 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/11

CPC classification number: H01L27/088 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/845 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/1104 ,  H01L27/1211

Abstract: A method is provided. The method includes forming a first to third gate lines on a substrate, the second gate line formed between the first and third gate lines; forming a gate isolation region to cut the first to third gate lines into two first sub gate lines, two second sub gate lines and two third sub gate lines, respectively; forming a first gate contact on one of the two first sub gate lines; forming a second gate contact on the two second sub gate lines; forming a third gate contact on one of the two third sub gate lines; forming a first metal line to connect the first and third gate contacts; and forming a second metal line. The first to third gate lines extend in a first direction, and the gate isolation region extends in a second direction different from the first direction.

公开(公告)号：US20140097493A1

公开(公告)日：2014-04-10

申请号：US14042900

申请日：2013-10-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-hoon BAEK ,  Sang-Kyu OH

IPC: H01L27/12

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/845 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/1211 ,  H01L29/6681

Abstract: A semiconductor integrated circuit (IC) may comprise at least one cell comprising at least one fin field-effect transistor (FET). The at least one cell may comprise a plurality of fins that extend in a first direction and are arranged in parallel to each other in a second direction that is perpendicular to the first direction. A size of the at least one cell in the second direction may correspond to a number and a pitch of the plurality of fins.

Abstract translation: 半导体集成电路（IC）可以包括至少一个包括至少一个鳍状场效应晶体管（FET）的单元。 至少一个电池可以包括沿着第一方向延伸并且沿垂直于第一方向的第二方向彼此平行布置的多个散热片。 第二方向上的至少一个单元的尺寸可以对应于多个翅片的数量和间距。

公开(公告)号：US20200152627A1

公开(公告)日：2020-05-14

申请号：US16746071

申请日：2020-01-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Hoon BAEK ,  Sun-Young PARK ,  Sang-Kyu OH ,  Ha-young KIM ,  Jung-Ho DO ,  Moo-Gyu BAE ,  Seung-Young LEE

IPC: H01L27/088 ,  H01L27/12 ,  H01L21/84 ,  H01L23/528 ,  H01L21/8234 ,  H01L27/11 ,  H01L27/02

Abstract: A system on chip includes first to third nanowires extending in a second direction, first to third gate lines respectively surrounding the first to third nanowires, each of the first to third gate lines extending in a first direction across the second direction, a gate isolation region cutting the first to third gate lines and extending in the second direction, a first gate contact formed on the second gate line arranged between the first gate line and the third gate line, and electrically connecting the cut second gate line, a second gate contact formed on the first gate line, a third gate contact formed on the third gate line, a first metal line electrically connecting the second gate contact and the third gate contact; and a second metal line electrically connected to the first gate contact.

公开(公告)号：US20160027703A1

公开(公告)日：2016-01-28

申请号：US14807220

申请日：2015-07-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Ho DO ,  Sanghoon BAEK ,  Sang-Kyu OH ,  Kwanyoung CHUN ,  Sunyoung PARK ,  Taejoong SONG

IPC: H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823871 ,  H01L27/0207 ,  H01L27/092

Abstract: Provided is a method of fabricating a semiconductor device with a field effect transistor. The method may include forming a first gate electrode and a second gate electrode extending substantially parallel to each other and each crossing a PMOSFET region on a substrate and an NMOSFET region on the substrate; forming an interlayered insulating layer covering the first gate electrode and the second gate electrode; patterning the interlayered insulating layer to form a first sub contact hole on the first gate electrode, the first sub contact hole being positioned between the PMOSFET region and the NMOSFET region, when viewed in a plan view; and patterning the interlayered insulating layer to form a first gate contact hole and to expose a top surface of the second gate electrode, wherein the first sub contact hole and the first gate contact hole form a single communication hole.

Abstract translation: 提供一种制造具有场效应晶体管的半导体器件的方法。 该方法可以包括形成基本上彼此平行延伸并且每个跨越衬底上的PMOSFET区域和衬底上的NMOSFET区域延伸的第一栅电极和第二栅电极; 形成覆盖所述第一栅电极和所述第二栅电极的层间绝缘层; 在第一栅电极上图形化层间绝缘层以形成第一子接触孔，当在平面图中观察时，第一子接触孔位于PMOSFET区和NMOSFET区之间; 以及图案化所述层间绝缘层以形成第一栅极接触孔并暴露所述第二栅电极的顶表面，其中所述第一子接触孔和所述第一栅极接触孔形成单个连通孔。