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    METHODS OF GENERATING INTEGRATED CIRCUIT LAYOUT USING STANDARD CELL LIBRARY
    2.
    发明申请
    METHODS OF GENERATING INTEGRATED CIRCUIT LAYOUT USING STANDARD CELL LIBRARY 有权
    使用标准单元库生成集成电路布局的方法

    公开(公告)号：US20160055285A1

    公开(公告)日：2016-02-25

    申请号：US14832325

    申请日：2015-08-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sang-hoon BAEK ,  Jae-woo SEO ,  Gi-young YANG ,  Dal-hee LEE ,  Sung-wee CHO

    IPC: G06F17/50

    CPC classification number: G06F17/5072 ,  G06F17/50 ,  G06F17/5068 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/06 ,  G06F2217/12 ,  G06F2217/78 ,  H01L21/823431 ,  H01L21/823821 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0886 ,  H01L29/6681

    Abstract: Methods of generating an integrated circuit layout include forming a standard cell by providing a first active area adjacent to a first cell boundary line. The first active area is spaced apart from the first cell boundary line by a first distance. A second active area is provided adjacent to a second cell boundary line. The second cell boundary line opposes the first cell boundary line. The second active area is spaced apart from the second cell boundary line by a second distance. Fins are formed on the first and second active areas. The fins extend in a first direction and parallel to one another in a second direction substantially perpendicular to the first direction. The first cell boundary line is parallel to the fins. The first distance and the second distance remain constant when a number of the fins on the first and second active areas is changed.

    Abstract translation: 生成集成电路布局的方法包括通过提供与第一单元边界线相邻的第一有源区来形成标准单元。 第一有效区域与第一细胞边界线隔开第一距离。 第二活动区域被设置成与第二单元边界线相邻。 第二细胞边界线与第一细胞边界线相反。 第二有效区域与第二细胞边界线间隔第二距离。 翅片形成在第一和第二活动区域上。 翅片在第一方向上延伸并且在基本上垂直于第一方向的第二方向上彼此平行。 第一个细胞边界线平行于翅片。 当第一和第二有效区域上的多个翅片改变时，第一距离和第二距离保持恒定。

    CELLS INCLUDING AT LEAST ONE FIN FIELD EFFECT TRANSISTOR AND SEMICONDUCTOR INTEGRATED CIRCUITS INCLUDING THE SAME
    3.
    发明申请
    CELLS INCLUDING AT LEAST ONE FIN FIELD EFFECT TRANSISTOR AND SEMICONDUCTOR INTEGRATED CIRCUITS INCLUDING THE SAME 有权
    包括至少一个FIN场效应晶体管和包括其中的半导体集成电路的电池

    公开(公告)号：US20140097493A1

    公开(公告)日：2014-04-10

    申请号：US14042900

    申请日：2013-10-01

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sang-hoon BAEK ,  Sang-Kyu OH

    IPC: H01L27/12

    CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/845 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/1211 ,  H01L29/6681

    Abstract: A semiconductor integrated circuit (IC) may comprise at least one cell comprising at least one fin field-effect transistor (FET). The at least one cell may comprise a plurality of fins that extend in a first direction and are arranged in parallel to each other in a second direction that is perpendicular to the first direction. A size of the at least one cell in the second direction may correspond to a number and a pitch of the plurality of fins.

    Abstract translation: 半导体集成电路（IC）可以包括至少一个包括至少一个鳍状场效应晶体管（FET）的单元。 至少一个电池可以包括沿着第一方向延伸并且沿垂直于第一方向的第二方向彼此平行布置的多个散热片。 第二方向上的至少一个单元的尺寸可以对应于多个翅片的数量和间距。

    INTEGRATED CIRCUIT AND SEMICONDUCTOR DEVICE
    4.
    发明申请
    INTEGRATED CIRCUIT AND SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20170133380A1

    公开(公告)日：2017-05-11

    申请号：US15409523

    申请日：2017-01-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ha-young KIM ,  Sung-we CHO ,  Tae-joong SONG ,  Sang-hoon BAEK

    IPC: H01L27/092 ,  G06F17/50 ,  H01L27/02 ,  H01L23/522 ,  H01L23/528

    CPC classification number: H01L27/0924 ,  G06F17/5077 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/092

    Abstract: An embodiment includes an integrated circuit comprising a standard cell, the standard cell comprising: first and second active regions having different conductivity types and extending in a first direction; first, second, and third conductive lines extending over the first and second active regions in a second direction substantially perpendicular to the first direction, and disposed parallel to each other; and a cutting layer extending in the first direction between the first and second active regions and separating the first conductive line into a first upper conductive line and a first lower conductive line, the second conductive line into a second upper conductive line and a second lower conductive line, and the third conductive line into a third upper conductive line and a third lower conductive line; wherein: the first upper conductive line and the third lower conductive line are electrically connected together; and the second upper conductive line and the second lower conductive line are electrically connected together.

    METHODS OF GENERATING INTEGRATED CIRCUIT LAYOUT USING STANDARD CELL LIBRARY
    6.
    发明申请
    METHODS OF GENERATING INTEGRATED CIRCUIT LAYOUT USING STANDARD CELL LIBRARY 审中-公开
    使用标准单元库生成集成电路布局的方法

    公开(公告)号：US20170011160A1

    公开(公告)日：2017-01-12

    申请号：US15271883

    申请日：2016-09-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sang-hoon BAEK ,  Jae-woo SEO ,  Gi-young YANG ,  Dal-hee LEE ,  Sung-wee CHO

    IPC: G06F17/50 ,  H01L27/02 ,  H01L23/528 ,  H01L27/088

    CPC classification number: G06F17/5072 ,  G06F17/50 ,  G06F17/5068 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/06 ,  G06F2217/12 ,  G06F2217/78 ,  H01L21/823431 ,  H01L21/823821 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0886 ,  H01L29/6681

    Abstract: Methods of generating an integrated circuit layout include forming a standard cell by providing a first active area adjacent to a first cell boundary line. The first active area is spaced apart from the first cell boundary line by a first distance. A second active area is provided adjacent to a second cell boundary line. The second cell boundary line opposes the first cell boundary line. The second active area is spaced apart from the second cell boundary line by a second distance. Fins are formed on the first and second active areas. The fins extend in a first direction and parallel to one another in a second direction substantially perpendicular to the first direction. The first cell boundary line is parallel to the fins. The first distance and the second distance remain constant when a number of the fins on the first and second active areas is changed.

    Abstract translation: 生成集成电路布局的方法包括通过提供与第一单元边界线相邻的第一有源区来形成标准单元。 第一有效区域与第一细胞边界线隔开第一距离。 第二活动区域被设置成与第二单元边界线相邻。 第二细胞边界线与第一细胞边界线相反。 第二有效区域与第二细胞边界线间隔第二距离。 翅片形成在第一和第二活动区域上。 翅片在第一方向上延伸并且在基本上垂直于第一方向的第二方向上彼此平行。 第一个细胞边界线平行于翅片。 当第一和第二有效区域上的多个翅片改变时，第一距离和第二距离保持恒定。

    FIN TRANSISTOR AND SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING THE SAME
    8.
    发明申请
    FIN TRANSISTOR AND SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING THE SAME 有权
    FIN晶体管和半导体集成电路，包括它们

    公开(公告)号：US20140077303A1

    公开(公告)日：2014-03-20

    申请号：US14026345

    申请日：2013-09-13

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sang-hoon BAEK

    IPC: H01L29/78 ,  G06F17/50

    CPC classification number: H01L29/785 ,  G06F17/5063 ,  G06F17/5081 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/6681

    Abstract: Provided are a fin transistor including a plurality of fins and a semiconductor integrated circuit including a plurality of fin transistors. A width of at least one fin of the plurality of fins is different from widths of the other fins, and each width of the plurality of fins is individually determined based on the electrical characteristics of the fin transistor.

    Abstract translation: 提供了包括多个鳍片的翅片晶体管和包括多个鳍式晶体管的半导体集成电路。 多个翅片中的至少一个翅片的宽度与其他翅片的宽度不同，并且基于鳍式晶体管的电特性单独确定多个翅片的每个宽度。

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