公开(公告)号：US20190129655A1

公开(公告)日：2019-05-02

申请号：US16023706

申请日：2018-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Raeyoung LEE ,  Hyunjung KIM ,  Sung-Bok LEE ,  Soyeong GWAK ,  Sang-wan NAM

IPC: G06F3/06 ,  G11C16/04 ,  G11C16/34 ,  G11C16/14 ,  G11C16/10 ,  G06F11/10 ,  G11C29/52

Abstract: A method of operating a memory controller, the memory controller configured to control a nonvolatile memory device, the nonvolatile memory device including a plurality of memory blocks. The method including detecting an invalid block among the plurality of memory blocks; determining an invalid pattern based on a state of the invalid block; and performing an operation on the invalid block such that the invalid block has the invalid pattern.

公开(公告)号：US20200119045A1

公开(公告)日：2020-04-16

申请号：US16707616

申请日：2019-12-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-wan NAM ,  Won-bo SHIM ,  Ji-ho CHO

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11524 ,  H01L29/10 ,  H01L27/1157 ,  H01L23/528 ,  G11C16/26 ,  G11C16/14 ,  G11C16/10 ,  G11C16/08 ,  G11C16/04

Abstract: A three-dimensional (3D) memory device having a plurality of vertical channel structures includes a first memory block, a second memory block, and a bit line. The first memory block includes first vertical channel structures extending in a vertical direction with respect to a surface of a substrate. The second memory block includes second vertical channel structures on the first vertical channel structures in the vertical direction and first and second string selection lines extending in a first horizontal direction and offset in the vertical direction. The bit line extends in the first horizontal direction between the first and second memory blocks and is shared by the first and second memory blocks. The second memory block may include first and second string selection transistors which are each connected to the bit line and the first string selection line and have different threshold voltages from each other.

公开(公告)号：US20190304994A1

公开(公告)日：2019-10-03

申请号：US16182047

申请日：2018-11-06

Applicant: Samsung Electronics Co.,Ltd.

Inventor： Sang-wan NAM ,  Won-bo SHIM ,  Ji-ho CHO

IPC: H01L27/11582 ,  H01L29/10 ,  G11C16/04 ,  H01L27/1157 ,  H01L23/528 ,  G11C16/14 ,  G11C16/10 ,  G11C16/26 ,  G11C16/08

Abstract: A three-dimensional (3D) memory device having a plurality of vertical channel structures includes a first memory block, a second memory block, and a bit line. The first memory block includes first vertical channel structures extending in a vertical direction with respect to a surface of a substrate. The second memory block includes second vertical channel structures on the first vertical channel structures in the vertical direction and first and second string selection lines extending in a first horizontal direction and offset in the vertical direction. The bit line extends in the first horizontal direction between the first and second memory blocks and is shared by the first and second memory blocks. The second memory block may include first and second string selection transistors which are each connected to the bit line and the first string selection line and have different threshold voltages from each other.