公开(公告)号：US20240153563A1

公开(公告)日：2024-05-09

申请号：US18545144

申请日：2023-12-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hye Ji LEE ,  Jin-Kyu KANG ,  Rae Young LEE ,  Se Jun PARK ,  Jae Duk LEE ,  Gu Yeon HAN

IPC: G11C16/16 ,  G11C11/56 ,  G11C16/04 ,  H10B41/27 ,  H10B43/27

CPC classification number: G11C16/16 ,  G11C11/5635 ,  G11C11/5671 ,  G11C16/0483 ,  H10B41/27 ,  H10B43/27

Abstract: A semiconductor memory device includes a source layer, a channel structure, gate electrodes on the source layer and spaced apart on a sidewall of the channel structure, and a common source line. The gate electrodes include a first word line group including first and second gate electrodes and a second word line group including third and fourth gate electrodes. The semiconductor memory device, in response to a voltage of the common source line reaching a target voltage, causes an inhibition voltage to be applied to the second word line group and an erase voltage to be applied to the first word line group in a first erase operation interval, and causes the inhibition voltage to be applied to the first word line group and the erase voltage to be applied to the second word line group in a second erase operation interval.

公开(公告)号：US20220076727A1

公开(公告)日：2022-03-10

申请号：US17233858

申请日：2021-04-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gu Yeon HAN ,  Jin-Kyu KANG ,  Rae Young LEE ,  Se Jun PARK ,  Jae Duk LEE

IPC: G11C11/4072 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4074

Abstract: A non-volatile memory device including: a memory cell array including non-volatile memory blocks connected to a plurality of word lines, a plurality of bit lines and a common source line; a common source line driver configured to supply a common source line voltage to the common source line; a page buffer unit configured to supply a bit line voltage to at least one of the plurality of bit lines; a control logic circuit configured to adjust the common source line voltage and the bit line voltage; and a channel initialization circuit, wherein the channel initialization circuit sets the common source line voltage and the bit line voltage to an initialization pulse, and the channel initialization circuit applies the initialization pulse between a plurality of read sections in which a read voltage is applied to at least two of the plurality of word lines.

公开(公告)号：US20240287668A1

公开(公告)日：2024-08-29

申请号：US18443517

申请日：2024-02-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Se Jun PARK ,  Do Hyung KIM ,  Se-Ung MIN ,  Ju Hwan PARK ,  Myung Seok SONG ,  Moon Seok JANG ,  Young Soo JUNG

IPC: C23C14/06 ,  C23C14/34 ,  C23C14/50 ,  C23C16/27 ,  C23C16/44 ,  H01L21/02 ,  H01L21/67 ,  H01L21/683

CPC classification number: C23C14/0611 ,  C23C14/3407 ,  C23C14/50 ,  C23C16/27 ,  C23C16/4408 ,  H01L21/02115 ,  H01L21/02266 ,  H01L21/67017 ,  H01L21/6833

Abstract: A DLC film deposition apparatus comprises a chamber in which processes are performed, a substrate in the chamber, the substrate having a first surface facing the top of the chamber, and a second surface opposite to the first surface, a holder in the chamber, the holder configured to support the substrate while being in contact with part of the second surface of the substrate, and a DLC film generator below the substrate, in the chamber, the DLC film generator configured to deposit a DLC film on the second surface of the substrate, wherein the DLC film is formed on the part of the second surface of the substrate that is not in contact with the holder.

公开(公告)号：US20230022639A1

公开(公告)日：2023-01-26

申请号：US17712238

申请日：2022-04-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hye Ji LEE ,  Jin-Kyu KANG ,  Rae Young LEE ,  Se Jun PARK ,  Jae Duk LEE ,  Gu Yeon HAN

IPC: G11C16/16 ,  H01L27/11556 ,  H01L27/11582 ,  G11C11/56 ,  G11C16/04

Abstract: A semiconductor memory device includes a source layer, a channel structure, gate electrodes on the source layer and spaced apart on a sidewall of the channel structure, and a common source line. The gate electrodes include a first word line group including first and second gate electrodes and a second word line group including third and fourth gate electrodes. The semiconductor memory device, in response to a voltage of the common source line reaching a target voltage, causes an inhibition voltage to be applied to the second word line group and an erase voltage to be applied to the first word line group in a first erase operation interval, and causes the inhibition voltage to be applied to the first word line group and the erase voltage to be applied to the second word line group in a second erase operation interval.