公开(公告)号：US20170207130A1

公开(公告)日：2017-07-20

申请号：US15386843

申请日：2016-12-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Se Jung PARK ,  Ju-Hyun KIM ,  Hoyoung KIM ,  Boun YOON ,  TaeYong KWON ,  Sangkyun KIM ,  Sanghyun PARK

IPC: H01L21/8238 ,  H01L21/306 ,  H01L27/092 ,  H01L21/3105

CPC classification number: H01L21/823807 ,  H01L21/30625 ,  H01L21/31053 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823878 ,  H01L27/092

Abstract: A patterning method for fabricating a semiconductor device includes forming, for example sequentially forming, a lower buffer layer, a first channel semiconductor layer, and a capping insulating layer on a substrate, forming an opening to penetrate the capping insulating layer and the first channel semiconductor layer and expose a portion of the lower buffer layer, forming a second channel semiconductor layer to fill the opening and include a first portion protruding above the capping insulating layer, performing a first CMP process to remove at least a portion of the first portion, removing the capping insulating layer, and performing a second CMP process to remove at least a portion of a second portion of the second channel semiconductor layer protruding above the first channel semiconductor layer.