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1.
公开(公告)号:US20240203980A1
公开(公告)日:2024-06-20
申请号:US18482680
申请日:2023-10-06
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Yongeun CHO , Hyunjeong ROH , Kibum KIM , Seonkyeong KIM , Hayoung KIM
IPC: H01L27/02 , H01L21/8234 , H01L23/48 , H02H9/04 , H01L23/00 , H01L25/065
CPC classification number: H01L27/0292 , H01L21/823475 , H01L23/481 , H01L27/0255 , H01L27/0266 , H02H9/046 , H01L24/05 , H01L24/16 , H01L24/17 , H01L25/0657 , H01L2224/0557 , H01L2224/16145 , H01L2224/16225 , H01L2224/17181 , H01L2225/06513 , H01L2225/06517 , H01L2225/06544
Abstract: A semiconductor device includes: a first I/O interface cell region having a plurality of first electrostatic discharge (ESD) diodes, a first driver and a first through silicon via (TSV) disposed therein and having first wiring patterns and first via patterns for electrically connecting the plurality of first ESD diodes, the first driver and the first TSV; and a second I/O interface cell region having a plurality of second ESD diodes, a second driver and a second TSV disposed therein and having second wiring patterns and second via patterns for electrically connecting the second driver, the second TSV and a subset of the plurality of second ESD diodes, wherein the second ESD diodes other than the subset are separated from the second driver and the second TSV.
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公开(公告)号:US20240203977A1
公开(公告)日:2024-06-20
申请号:US18475881
申请日:2023-09-27
Applicant: Samsung Electronics Co., Ltd.
Inventor: Yongeun CHO , Kibum KIM , Seonkyeong KIM , Hayoung KIM , Hyunjeong ROH
CPC classification number: H01L27/0255 , H01L23/481 , H01L27/0207
Abstract: A semiconductor device may include a substrate including a Keep-Out Zone (KOZ) and a layout finishing cell region, a through silicon via (TSV) penetrating the substrate and surrounded by the KOZ; an ESD diode on an upper surface of the substrate, a driver circuit, gate structures, and metal wirings electrically connecting the TSV, the ESD diode, and the driver circuit. The layout finishing cell region may surround the KOZ and the ESD diode. The driver circuit may be adjacent to and outside the layout finishing cell region. The substrate may include active regions extending from an end inside the layout finishing cell region. The gate structures may intersect the active regions to form semiconductor components. The driver circuit may include at least some of the semiconductor components.
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