SEMICONDUCTOR PACKAGE
    1.
    发明公开

    公开(公告)号:US20240258224A1

    公开(公告)日:2024-08-01

    申请号:US18421440

    申请日:2024-01-24

    Abstract: A semiconductor package includes a package-bottom redistribution structure at a lower side of a package and including a conductive line, an upper semiconductor chip at an upper side of the package, an upper back end of line (BEOL) layer, at a lower side of the upper semiconductor chip, and including a conductive line, a lower semiconductor chip below the upper semiconductor chip, where a horizontal width of the lower semiconductor chip is less than a horizontal width of the upper semiconductor chip, and where the upper semiconductor chip overlaps at least a portion of the lower semiconductor chip, a lower BEOL layer at a lower side of the lower semiconductor chip and including a conductive line, a passivation layer on an upper surface of the lower semiconductor chip, and a through silicon via (TSV) structure penetrating the passivation layer and the lower semiconductor chip.

    SEMICONDUCTOR PACKAGE INCLUDING SEMICONDUCTOR CHIP HAVING THROUGH-ELECTRODE

    公开(公告)号:US20240194575A1

    公开(公告)日:2024-06-13

    申请号:US18380042

    申请日:2023-10-13

    Abstract: A semiconductor package includes a first semiconductor chip including a first bonding layer, the first bonding layer including a first chip pad and a first insulating layer covering a side surface of the first chip pad, a second semiconductor chip disposed below the first semiconductor chip and including a substrate having front and rear surfaces, the front surface forming a second bonding layer, and through-electrodes passing through the substrate and having protrusions protruding from the rear surface, the second bonding layer including a second chip pad contacting the first chip pad and a second insulating layer covering a side surface of the second chip pad, a redistribution layer disposed below the second semiconductor chip and electrically connected to the second semiconductor chip, vias disposed between the redistribution layer and the first semiconductor chip and disposed around the second semiconductor chip, and an encapsulant surrounding the second semiconductor chip, the redistribution layer, and the vias. The encapsulant may be in contact with the protrusions of the through-electrodes.

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