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公开(公告)号：US20180096947A1
公开(公告)日：2018-04-05
申请号：US15608747
申请日：2017-05-30
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： KISEOK LEE , Sooho Shin , Juik Lee , Jun Ho Lee , Kwangmin Kim , Ilyoung Moon , Jemin Park , Bumseok Seo , Chan-Sic Yoon , Hoin Lee
IPC: H01L23/544 , H01L27/108
CPC classification number: H01L23/544 , H01L27/10814 , H01L27/10823 , H01L27/10876 , H01L27/10885 , H01L27/10894 , H01L27/10897 , H01L2223/5442 , H01L2223/54426 , H01L2223/5446
Abstract: A semiconductor device includes an alignment key on a substrate. The alignment key includes a first sub-alignment key pattern with a first conductive pattern, a second conductive pattern, and a capping dielectric pattern that are sequentially stacked on the substrate, an alignment key trench that penetrates at least a portion of the first sub-alignment key pattern, and a lower conductive pattern in the alignment key trench. The alignment key trench includes an upper trench that is provided in the capping dielectric pattern that has a first width, and a lower trench that extends downward from the upper trench and that has a second width less than the first width. The lower conductive pattern includes sidewall conductive patterns that are separately disposed on opposite sidewalls of the lower trench.
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公开(公告)号：US12080663B2
公开(公告)日：2024-09-03
申请号：US18377530
申请日：2023-10-06
Applicant: Samsung Electronics Co., Ltd.
Inventor： Minjung Choi , Sooho Shin , Yeonjin Lee , Junghoon Han
CPC classification number: H01L24/05 , H01L21/561 , H01L24/13 , H01L24/73 , H01L24/96 , H01L2224/0401 , H01L2224/12105 , H01L2224/13099 , H01L2224/81801 , H01L2924/1304 , H01L2924/18162
Abstract: A semiconductor device includes an interlayer insulating layer disposed on a substrate; a plurality of middle interconnections disposed in the interlayer insulating layer; a pad disposed on the interlayer insulating layer; an upper interconnection disposed on the interlayer insulating layer; a protective insulating layer covering an edge of the pad, the upper interconnection, and a horizontal gap between the pad and the upper interconnection, the protective insulating layer having an opening on the pad; and a bump disposed on the pad, the bump extending on the protective insulating layer and overlapping the upper interconnection from a top-down view. At least one of the plurality of middle interconnections from among middle interconnections vertically closest to the pad has a first vertical thickness, the pad has a second vertical thickness that is twice to 100 times the first vertical thickness, a length of the gap between the pad and the upper interconnection is 1 μm or more, and an upper surface of the protective insulating layer is planar.
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公开(公告)号：US11723191B2
公开(公告)日：2023-08-08
申请号：US17192084
申请日：2021-03-04
Applicant: Samsung Electronics Co., Ltd.
Inventor： Minsu Choi , Myeong-Dong Lee , Hyeon-Woo Jang , Keunnam Kim , Sooho Shin , Yoosang Hwang
IPC: H10B12/00
CPC classification number: H10B12/34 , H10B12/0335 , H10B12/053 , H10B12/315
Abstract: Disclosed are a semiconductor memory device and a method of fabricating the same. The device includes a substrate including an active pattern with doped regions, a gate electrode crossing the active pattern between the doped regions, a bit line crossing the active pattern and being electrically connected to one of the doped regions, a spacer on a side surface of the bit line, a first contact coupled to another of the doped regions and spaced apart from the bit line with the spacer interposed therebetween, a landing pad on the first contact, and a data storing element on the landing pad. The another of the doped regions has a top surface, an upper side surface, and a curved top surface that extends from the top surface to the upper side surface. The first contact is in contact with the curved top surface and the upper side surface.
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公开(公告)号：US11557556B2
公开(公告)日：2023-01-17
申请号：US17328365
申请日：2021-05-24
Applicant: Samsung Electronics Co., Ltd.
Inventor： Minjung Choi , Sooho Shin , Yeonjin Lee , Junghoon Han
Abstract: A semiconductor device includes an interlayer insulating layer disposed on a substrate; a plurality of middle interconnections disposed in the interlayer insulating layer; a pad disposed on the interlayer insulating layer; an upper interconnection disposed on the interlayer insulating layer; a protective insulating layer covering an edge of the pad, the upper interconnection, and a horizontal gap between the pad and the upper interconnection, the protective insulating layer having an opening on the pad; and a bump disposed on the pad, the bump extending on the protective insulating layer and overlapping the upper interconnection from a top-down view. At least one of the plurality of middle interconnections from among middle interconnections vertically closest to the pad has a first vertical thickness, the pad has a second vertical thickness that is twice to 100 times the first vertical thickness, a length of the gap between the pad and the upper interconnection is 1 μm or more, and an upper surface of the protective insulating layer is planar.
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公开(公告)号：US20220028860A1
公开(公告)日：2022-01-27
申请号：US17192084
申请日：2021-03-04
Applicant: Samsung Electronics Co., Ltd.
Inventor： Minsu Choi , Myeong-Dong Lee , Hyeon-Woo Jang , Keunnam Kim , Sooho Shin , Yoosang Hwang
IPC: H01L27/108
Abstract: Disclosed are a semiconductor memory device and a method of fabricating the same. The device includes a substrate including an active pattern with doped regions, a gate electrode crossing the active pattern between the doped regions, a bit line crossing the active pattern and being electrically connected to one of the doped regions, a spacer on a side surface of the bit line, a first contact coupled to another of the doped regions and spaced apart from the bit line with the spacer interposed therebetween, a landing pad on the first contact, and a data storing element on the landing pad. The another of the doped regions has a top surface, an upper side surface, and a curved top surface that extends from the top surface to the upper side surface. The first contact is in contact with the curved top surface and the upper side surface.
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Patent Agency Ranking
公开(公告)号：US11817408B2
公开(公告)日：2023-11-14
申请号：US18093880
申请日：2023-01-06
Applicant: Samsung Electronics Co., Ltd.
Inventor： Minjung Choi , Sooho Shin , Yeonjin Lee , Junghoon Han
CPC classification number: H01L24/05 , H01L21/561 , H01L24/13 , H01L24/73 , H01L24/96 , H01L2224/0401 , H01L2224/12105 , H01L2224/13099 , H01L2224/81801 , H01L2924/1304 , H01L2924/18162
Abstract: A semiconductor device includes an interlayer insulating layer disposed on a substrate; a plurality of middle interconnections disposed in the interlayer insulating layer; a pad disposed on the interlayer insulating layer; an upper interconnection disposed on the interlayer insulating layer; a protective insulating layer covering an edge of the pad, the upper interconnection, and a horizontal gap between the pad and the upper interconnection, the protective insulating layer having an opening on the pad; and a bump disposed on the pad, the bump extending on the protective insulating layer and overlapping the upper interconnection from a top-down view. At least one of the plurality of middle interconnections from among middle interconnections vertically closest to the pad has a first vertical thickness, the pad has a second vertical thickness that is twice to 100 times the first vertical thickness, a length of the gap between the pad and the upper interconnection is 1 μm or more, and an upper surface of the protective insulating layer is planar.
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公开(公告)号：US20230337415A1
公开(公告)日：2023-10-19
申请号：US18337134
申请日：2023-06-19
Applicant: Samsung Electronics Co., Ltd.
Inventor： Minsu Choi , Myeong-Dong Lee , Hyeon-Woo Jang , Keunnam Kim , Sooho Shin , Yoosang Hwang
IPC: H10B12/00
CPC classification number: H10B12/34 , H10B12/053 , H10B12/315 , H10B12/0335
Abstract: Disclosed are a semiconductor memory device and a method of fabricating the same. The device includes a substrate including an active pattern with doped regions, a gate electrode crossing the active pattern between the doped regions, a bit line crossing the active pattern and being electrically connected to one of the doped regions, a spacer on a side surface of the bit line, a first contact coupled to another of the doped regions and spaced apart from the bit line with the spacer interposed therebetween, a landing pad on the first contact, and a data storing element on the landing pad. The another of the doped regions has a top surface, an upper side surface, and a curved top surface that extends from the top surface to the upper side surface. The first contact is in contact with the curved top surface and the upper side surface.
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公开(公告)号：US10332842B2
公开(公告)日：2019-06-25
申请号：US16026937
申请日：2018-07-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kiseok Lee , Sooho Shin , Juik Lee , Jun Ho Lee , Kwangmin Kim , Ilyoung Moon , Jemin Park , Bumseok Seo , Chan-Sic Yoon , Hoin Lee
IPC: H01L23/544 , H01L27/108
Abstract: A semiconductor device includes an alignment key on a substrate. The alignment key includes a first sub-alignment key pattern with a first conductive pattern, a second conductive pattern, and a capping dielectric pattern that are sequentially stacked on the substrate, an alignment key trench that penetrates at least a portion of the first sub-alignment key pattern, and a lower conductive pattern in the alignment key trench. The alignment key trench includes an upper trench that is provided in the capping dielectric pattern that has a first width, and a lower trench that extends downward from the upper trench and that has a second width less than the first width. The lower conductive pattern includes sidewall conductive patterns that are separately disposed on opposite sidewalls of the lower trench.
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公开(公告)号：US20240397705A1
公开(公告)日：2024-11-28
申请号：US18391993
申请日：2023-12-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sooho Shin , Jihoon Chang
IPC: H10B12/00
Abstract: A semiconductor device includes a device isolation pattern defining active portions extending in a first direction, a first bit line intersecting the active portions in a second direction, a second bit line spaced apart from the first bit line in a third direction, bit line capping patterns on the bit lines, a storage node contact between the bit lines, a diffusion barrier layer on sidewalls of bit lines and on a top of the storage node contact, and a landing pad on the diffusion barrier layer. A first upper end of the diffusion barrier layer on the sidewall of the first bit line is lower than the bit line capping patterns, and a second upper end of the diffusion barrier layer on the sidewall of the second bit line is lower than the first upper end.
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公开(公告)号：US11049827B2
公开(公告)日：2021-06-29
申请号：US16795658
申请日：2020-02-20
Applicant: Samsung Electronics Co., Ltd.
Inventor： Minjung Choi , Sooho Shin , Yeonjin Lee , Junghoon Han
Abstract: A semiconductor device includes an interlayer insulating layer disposed on a substrate; a plurality of middle interconnections disposed in the interlayer insulating layer; a pad disposed on the interlayer insulating layer; an upper interconnection disposed on the interlayer insulating layer; a protective insulating layer covering an edge of the pad, the upper interconnection, and a horizontal gap between the pad and the upper interconnection, the protective insulating layer having an opening on the pad; and a bump disposed on the pad, the bump extending on the protective insulating layer and overlapping the upper interconnection from a top-down view. At least one of the plurality of middle interconnections from among middle interconnections vertically closest to the pad has a first vertical thickness, the pad has a second vertical thickness that is twice to 100 times the first vertical thickness, a length of the gap between the pad and the upper interconnection is 1 μm or more, and an upper surface of the protective insulating layer is planar.
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