公开(公告)号：US10691455B2

公开(公告)日：2020-06-23

申请号：US15684573

申请日：2017-08-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tejash M. Shah ,  Srinivasan S. Iyer ,  David C. Tannenbaum

IPC: G06F9/30 ,  G06F9/38 ,  G06F1/3234 ,  G06F9/32 ,  G06T1/20 ,  G06F30/34 ,  G05B19/4097 ,  G06F30/327 ,  G06F119/06

Abstract: A method and apparatus are provided. The method includes executing a plurality of threads in a temporal dimension, executing a plurality of threads in a spatial dimension, determining a branch target address for each of the plurality of threads in the temporal dimension and the plurality of threads in the spatial dimension, and comparing each of the branch target addresses to determine a minimum branch target address, wherein the minimum branch target address is a minimum value among branch target addresses of each of the plurality of threads.

公开(公告)号：US20180341489A1

公开(公告)日：2018-11-29

申请号：US15684573

申请日：2017-08-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tejash M. Shah ,  Srinivasan S. Iyer ,  David C. Tannenbaum

IPC: G06F9/30 ,  G06F1/32 ,  G06F17/50

Abstract: A method and apparatus are provided. The method includes executing a plurality of threads in a temporal dimension, executing a plurality of threads in a spatial dimension, determining a branch target address for each of the plurality of threads in the temporal dimension and the plurality of threads in the spatial dimension, and comparing each of the branch target addresses to determine a minimum branch target address, wherein the minimum branch target address is a minimum value among branch target addresses of each of the plurality of threads.

公开(公告)号：US20190384600A1

公开(公告)日：2019-12-19

申请号：US16127104

申请日：2018-09-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mitchell K. Alsup ,  David C. Tannenbaum ,  Derek Lentz ,  Srinivasan S. Iyer ,  Christopher J. Goodman

IPC: G06F9/30 ,  G06T15/80 ,  G06F9/38 ,  G06T15/00 ,  G06T1/20 ,  G06T1/60

Abstract: A system and method for binding instructions to a graphical processing unit (GPU) includes a GPU configured to receive bindlessly compiled instructions and interpret the bindlessly compiled instruction at runtime to identify a needed conversion The GPU generates a conversion information based on the bindlessly compiled instruction and needed conversion and converts the bindlessly compiled instruction according to the conversion information to generate a bound format instruction. The GPU may then execute the bound format instruction.

公开(公告)号：US10360034B2

公开(公告)日：2019-07-23

申请号：US15633746

申请日：2017-06-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： David C. Tannenbaum ,  Srinivasan S. Iyer ,  Mitchell K. Alsup

IPC: G06F9/30 ,  G06F9/38 ,  G06T1/20 ,  G06T1/60

Abstract: A graphics processing unit may include a register file memory, a processing element (PE) and a load-store unit (LSU). The register file memory includes a plurality of registers. The PE is coupled to the register file memory and processes at least one thread of a vector of threads of a graphical application. Each thread in the vector of threads are processed in a non-stalling manner. The PE stores data in a first predetermined set of the plurality of registers in the register file memory that has been generated by processing the at least one thread and that is to be routed to a first stallable logic unit that is external to the PE. The LSU is coupled to the register file memory, and the LSU accesses the data in the first predetermined set of the plurality of registers and routes to the first stallable logic unit.