Heavy-weight/light-weight GPU shader core pair architecture

    公开(公告)号:US11120603B2

    公开(公告)日:2021-09-14

    申请号:US16538819

    申请日:2019-08-12

    摘要: A shader core includes a first processing element (PE), a second processing element, a register file and a warp sequencing unit. The first PE includes a first predetermined number of execution units, and the second PE includes a second predetermined number of execution units in which the second predetermined number of execution units is less than the first predetermined number of execution units. The register file shared by the first PE and the second PE. The warp sequencer unit (WSQ) is coupled to the first PE and to the second PE and schedules an instruction trace to execute on the first PE or the second PE based on information contained in a trace header of the instruction trace. The information contained in the trace header indicates whether the instruction trace is executable on the second PE.

    POWER SAVING BRANCH MODES IN HARDWARE
    3.
    发明申请

    公开(公告)号:US20180341489A1

    公开(公告)日:2018-11-29

    申请号:US15684573

    申请日:2017-08-23

    IPC分类号: G06F9/30 G06F1/32 G06F17/50

    摘要: A method and apparatus are provided. The method includes executing a plurality of threads in a temporal dimension, executing a plurality of threads in a spatial dimension, determining a branch target address for each of the plurality of threads in the temporal dimension and the plurality of threads in the spatial dimension, and comparing each of the branch target addresses to determine a minimum branch target address, wherein the minimum branch target address is a minimum value among branch target addresses of each of the plurality of threads.